82583V Datasheet, PDF (87/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.1.3.9
6.1.3.10
6.1.4
6.1.4.1
Error Forwarding
If a Transaction Layer Protocol (TLP) is received with an error-forwarding trailer, the
packet is dropped and not delivered to its destination. The 82583V does not initiate any
additional master requests for that PCI function until it detects an internal reset or
software. Software is able to access device registers after such a fault.
System logic is expected to trigger a system-level interrupt to inform the operating
system of the problem. The operating system can then stop the process associated
with the transaction, re-allocate memory instead of the faulty area, etc.
Master Disable
System software can disable master accesses on the PCIe link by either clearing the
PCI Bus Master bit or by bringing the function into a D3 state. From that time on, the
82583V must not issue master accesses for this function. Due to the full-duplex nature
of PCIe, and the pipelined design in the 82583V, it might happen that multiple requests
from several functions are pending when the master disable request arrives. The
protocol described in this section insures that a function does not issue master requests
to the PCIe link after its master enable bit is cleared (or after entry to D3 state).
Two configuration bits are provided for the handshake between the device function and
its driver:
• PCIe Master Disable bit in the Device Control (CTRL) register - When the PCIe
Master Disable bit is set, the 82583V blocks new master requests. The 82583V then
proceeds to issue any pending requests by this function. This bit is cleared on
master reset (Internal Power On Reset all the way to a software reset) to enable
master accesses.
• PCIe Master Enable Status bits in the Device Status register - Cleared by the
82583V when the PCIe Master Disable bit is set and no master requests are
pending by the relevant function, set otherwise.
Software Note:
— The software device driver sets the PCIe Master Disable bit when notified of a
pending master disable (or D3 entry). The 82583V then blocks new requests
and proceeds to issue any pending requests by this function. The software
device driver then polls the PCIe Master Enable Status bit. Once the bit is
cleared, it is guaranteed that no requests are pending from this function. The
software device driver might time out if the PCIe Master Enable Status bit is not
cleared within a given time.
— The PCIe Master Disable bit must be cleared to enable a master request to the
PCIe link. This can be done either through reset or by the software device
driver.
Flow Control
Flow Control Rules
The 82583V only implements the default Virtual Channel (VC0). A single set of credits
is maintained for VC0.
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