82583V Datasheet, PDF (316/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
10.1.5.1.7
Link CAP, Offset 0xEC, (RO)
This register identifies PCIe link-specific capabilities. This is a read-only register.
Bits
R/W
3:0
RO
9:4
RO
11:10 RO
14:12 RO
17:15 RO
18
RO
19
RO
20
RO
23:21 RO
31:24 HwInit
Default
Description
0001b
Max Link Speed
The 82583V indicates a maximum link speed of 2.5 Gb/s.
0x01
Max Link Width
Indicates the maximum link width. The 82583V supports x1 lane link.
Defined encoding:
000001b x1.
All other values - Reserved.
Active State Link PM Support
Indicates the level of active state power management supported in the
82583V. Defined encodings are:
11b
00b = No ASPM support.
01b = L0s supported.
10b = L1 supported.
11b = L0s and L1 supported.
This field is loaded from the NVM PCIe Init Configuration 3 word 0x1A.
001b
(64-
128 ns)
L0s Exit Latency
Indicates the exit latency from L0s to L0 state. This field is loaded from the
NVM PCIe Init Configuration 1 word 0x18 (two values for common PCIe clock
or separate PCIe clock.
000b = Less than 64 ns.
001b = 64 ns – 128 ns.
010b = 128 ns – 256 ns.
011b = 256 ns - 512 ns.
100b = 512 ns - 1 μs.
101b = 1 μs – 2 μs.
110b = 2 μs – 4 μs.
111b = Reserved.
If the 82583V uses a common clock - PCIe Init Config 1 bits [2:0], if the
82583V uses a separate clock - PCIe Init Config 1 bits [5:3].
110b
(32-64 μs)
L1 Exit Latency
Indicates the exit latency from L1 to L0 state. This field is loaded from the
NVM PCIe Init Configuration 1 word 0x18.
000b = Less than 1 μs.
001b = 1 μs - 2 μs.
010b = 2 μs - 4 μs.
011b = 4 μs - 8 μs.
100b = 8 μs - 16 μs.
101b = 16 μs - 32 μs.
110b = 32 μs - 64 μs.
111b = L1 transition not supported.
0b
Reserved.
0b
Surprise Down Error Reporting Capable.
0b
Data Link Layer Link Active Reporting Capable.
000b
Reserved.
Port Number
0x0
The PCIe port number for the given PCIe link. Field is set in the link training
phase.
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