82583V Datasheet, PDF (178/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Power Management and Delivery
PCIe Reference
Clock
PCIe PwrGd
Reading EEPROM
D3 write
PHY Reset
1
PCIe Link L0
Wake Up Enabled
PHY Power State full
DState D0a
D0 Write
2
3
tee
td0me
m
Auto
Ext.
6 ^{Memory Access Enable}
Read
Conf.
5
7
Any mode
L1
power-managed
D3
L0
4
APM
power-
managed
D0u
full
D0
Figure 41.
Table 46.
D3hot Transition Timing Diagram
Notes to D3hot Timing Diagram
Note
Description
1
Writing 11b to the Power State field of the PMCSR transitions the 82583V to D3.
2
The system keeps the 82583V in D3 state for an arbitrary amount of time.
3
To exit D3 state the system writes 00b to the Power State field of the PMCSR.
4
APM wake up mode can be enabled based on what is read in the NVM.
5
After reading the NVM, reset to the PHY is de-asserted. The PHY operates at reduced-speed if APM
wake up is enabled, else powered-down.
6
The system can delay an arbitrary time before enabling memory access.
Writing a 1b to the Memory Access Enable bit or to the I/O Access Enable bit in the PCI Command
7
register transitions the 82583V from D0u to D0 state and returns the PHY to full-power/speed
operation.
8.4.5.2
Transition From D0a to D3 and Back with PE_RST_N
Figure 42 shows the 82583V’s reaction to a D3 transition.
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