82583V Datasheet, PDF (54/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Initialization
4.6.5
4.6.5.1
4.6.6
Receive Initialization
Program the receive address register per the station address. This can come from the
NVM or from any other means, for example, on some systems, this comes from the
system EEPROM not the NVM on a Network Interface Card (NIC).
Set up the Multicast Table Array (MTA) per software. This generally means zeroing all
entries initially and adding in entries as requested.
Program the interrupt mask register to pass any interrupt that the software device
driver cares about. Suggested bits include RXT, RXO, RXDMT and LSC. There is no
reason to enable the transmit interrupts.
Program RCTL with appropriate values. If initializing it at this stage, it is best to leave
the receive logic disabled (EN = 0b) until the receive descriptor ring has been
initialized. If VLANs are not used, software should clear the VFE bit. Then there is no
need to initialize the VFTA array. Select the receive descriptor type. Note that if using
the header split RX descriptors, tail and head registers should be incremented by two
per descriptor.
Initialize the Receive Control Register
To properly receive packets requires simply that the receiver is enabled. This should be
done only after all other setup is accomplished. If software uses the Receive Descriptor
Minimum Threshold Interrupt, that value should be set.
Do the following for the receive queue:
• Allocate a region of memory for the receive descriptor list.
• Receive buffers of appropriate size should be allocated and pointers to these
buffers should be stored in the descriptor ring.
• Program the descriptor base address with the address of the region.
• Set the length register to the size of the descriptor ring.
• If needed, program the head and tail registers. Note: the head and tail pointers are
initialized (by hardware) to zero after a power-on or a software-initiated device
reset.
• The tail pointer should be set to point one descriptor beyond the end.
Transmit Initialization
Program the TXDCTL register with the desired TX descriptor write-back policy.
Suggested values are:
• GRAN = 1b (descriptors)
• WTHRESH = 1b
• All other fields 0b.
Program the TCTL register. Suggested configuration:
• CT = 0x0F (16d collision)
• COLD: HDX = 511 (0x1FF); FDX = 63 (0x03F)
• PSP = 1b
• EN=1b
• All other fields 0b
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