82583V Datasheet, PDF (190/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
The IODATA register may be written as a byte, word, or Dword access when the
IOADDR register contains a value for the Flash (such as, 0x80000-0xFFFFF). In this
case, the value in IOADDR must be properly aligned to the data value. The following
table lists the supported configurations:
Note:
Note:
Note:
9.1.1.4.3
Access Type
Byte (8 bit)
Word (16 bit)
Dword (32 bit)
82583V IOADDR Register Bits
[1:0]
00b
01b
10b
11b
00b
10b
00b
Target IODATA Access BE[3:0]#
bits in Data Phase
1110b
1101b
1011b
0111b
1100b
0011b
0000b
Software might have to implement non-obvious code to access the Flash, a byte, or
word at a time. Example code that reads a Flash byte is shown here to illustrate the
impact of the previous table:
char *IOADDR;
char *IODATA;
IOADDR = IOBASE + 0;
IODATA = IOBASE + 4;
*(IOADDR) = Flash_Byte_Address;
Read_Data = *(IODATA + (Flash_Byte_Address % 4));
Reads to IODATA of any size return a Dword of data. However, the chipset or CPU might
only return a subset of that Dword.
For software programmers, the IN and OUT instructions must be used to cause I/O
cycles to be used on the PCIe bus. Where 32-bit quantities are required on writes, the
source register of the OUT instruction must be EAX (the only 32-bit register supported
by the OUT command).
Writes and reads to IODATA when the IOADDR register value is in an undefined range
(0x20000-0x7FFFC) should not be performed. Results cannot be determined.
There are no special software timing requirements on accesses to IOADDR or IODATA.
All accesses are immediate except when data is not readily available or acceptable. In
this case, the 82583V delays the results through normal bus methods (for example,
split transaction or transaction retry).
Because a register/memory/Flash read or write takes two I/O cycles to complete,
software must provide a guarantee that the two I/O cycles occur as an atomic
operation. Otherwise, results can be non-deterministic from the software viewpoint.
Undefined I/O Offsets
I/O offsets 0x08 through 0x1F are considered to be reserved offsets with the I/O
window. Dword reads from these addresses return 0xFFFF; writes to these addresses
are discarded.
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