82583V Datasheet, PDF (81/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.1.1
A packet is the fundamental unit of information exchange and the protocol includes a
message space to replace the number of side-band signals found on many of today’s
buses. This movement of hard-wired signals from the physical layer to messages within
the transaction layer enables easy and linear physical layer width expansion for
increased bandwidth.
The common base protocol uses split transactions along with several mechanisms that
are included to eliminate wait states and to optimize the reordering of transactions to
further improve system performance.
Architecture, Transaction, and Link Layer Properties
• Split transaction, packet-based protocol
• Common flat address space for load/store access (such as a PCI addressing
model):
— Memory address space of 32 bits to enable compact packet header (must be
used to access addresses below 4 GB)
— Memory address space of 64 bits using extended packet header
• Transaction layer mechanisms:
— PCI-X style relaxed ordering
— Optimizations for no-snoop transactions
• Credit-based flow control
• Packet sizes/formats:
— Maximum packet size supports 128- and 256-byte data payload
— Maximum read request size of 4 KB
• Reset/initialization:
— Frequency/width/profile negotiation performed by hardware
• Data integrity support:
— Using CRC-32 for transaction layer packets
• Link layer retry for recovery following error detection:
— Using CRC-16 for link layer messages
• No retry following error detection:
— 8b/10b encoding with running disparity
• Software configuration mechanism:
— Uses PCI configuration and bus enumeration model
— PCIe-specific configuration registers mapped via PCI extended capability
mechanism
• Baseline messaging:
— In-band messaging of formerly side-band legacy signals (such as interrupts)
— System-level power management supported via messages
• Power Management (PM):
— Full PCI PM support
— Wake capability from D3cold state
— Compliant with ACPI 2.0, PCI PM software model
— Active state power management (transparent to software including ACPI)
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