82583V Datasheet, PDF (94/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
Table 33. DLLPs initiated by The 82583V
6.1.7.3
6.1.8
6.1.8.1
6.1.8.2
6.1.8.3
Remarks¹
ACK
NAK
PM_Enter_L1
PM_Enter_L23
PM_Active_State_Request_L1
InitFC1-P
InitFC1-NP
InitFC1-Cpl
InitFC2-P
InitFC2-NP
InitFC2-Cpl
UpdateFC-P
UpdateFC-NP
v2v1v0 = 000
v2v1v0 = 000
v2v1v0 = 000
v2v1v0 = 000
v2v1v0 = 000
v2v1v0 = 000
v2v1v0 = 000
v2v1v0 = 000
1. UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation.
Remarks
Transmit EDB Nullifying
In case of a retrain necessity, there is a need to guarantee that no abrupt termination
of the Tx packet happens. For this reason, early termination of the transmitted packet
is possible. This is done by appending the EDB to the packet.
PHY
Link Width
The 82583V supports a link width of x1 only.
Polarity Inversion
If polarity inversion is detected, the receiver must invert the received data.
During the training sequence, the receiver looks at Symbols 6-15 of TS1 and TS2 as the
indicator of lane polarity inversion (D+ and D- are swapped). If lane polarity inversion
occurs, the TS1 Symbols 6-15 received are D21.5 as opposed to the expected D10.2.
Similarly, if lane polarity inversion occurs, Symbols 6-15 of the TS2 ordered set are
D26.5 as opposed to the expected 5D5.2. This provides the clear indication of lane
polarity inversion.
L0s Exit Latency
The number of FTS sequences (N_FTS), sent during L1 exit, is loaded from the NVM
into an 8-bit read-only register.
94