82583V Datasheet, PDF (20/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Pin Interface
Table 9.
2.3.5
PHY Pins
Symbol
XTAL1
XTAL2
ATEST_P
ATEST_N
RSET
Lead #
Type
Op
Mode
Name and Function
XTAL In/Out
43
A-In
Input/ These pins can be driven by an external 25 MHz crystal or
42
A-Out ^Output driven by an external MOS level 25 MHz oscillator. Used to
drive the PHY.
45
46
A-out
Output
Positive side of the high speed differential debug port for
the PHY.
PHY Termination
48
A
Bias
This pin should be connected through a 4.99 KΩ +-1%
resister to ground.
Miscellaneous and Test Pins
Table 10.
Miscellaneous and Test Pins
Symbol
DEV_OFF_N
Lead #
28
TEST_EN
29
AUX_PWR/
JTAG_TCK
39
NVMT/JTAG_TMS 38
JTAG_TDI
40
Type
Op
Mode
Name and Function
This is a 3.3 V dc input signal. Asserting DEV_OFF_N
In
Input puts the 82583V in device disable mode. Note that
this pin is asynchronous.
Enables Test Mode
Test pins are overloaded on the functional signals as
In
Input
described in the pin description text of this section.
The pin is active high.
Note: This pin should be externally pulled down for
normal operation.
Auxiliary Power Indication.
AUX_PWR is supported when sampled high and
In
Input
should be connected using a resistor
JTAG Clock Input
Note: The AUX_PWR/JTAG_TCK port pin includes an
internal pull-down resistor.
NVM Type
The NVM is Flash when sampled LOW and EEPROM
when sampled HIGH.
In
Input ^{JTAG TMS Input.}
Note: The NVMT/JTAG_TMS port pin includes an
internal pull-up resistor. Also note that the internal
pull-up is disconnected during startup. As a result,
NVMT MUST be connected externally.
JTAG TDI Input
In
Input Note: The JTAG_TDI port pin includes an internal
pull-up resistor.
20