82583V Datasheet, PDF (128/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
When the number of descriptors specified by RXDCTL.WTHRESH have been used, they
are written back, regardless of cache line alignment. It is therefore recommended that
WTHRESH be a multiple of cache line size. When a receive timer (RADV or RDTR)
expires, all used descriptors are forced to be written back prior to initiating the
interrupt, for consistency. Software might explicitly flush accumulated descriptors by
writing the RDTR register with the high order bit (FPD) set.
7.1.7.2
Note:
Null Descriptor Padding
Hardware stores no data in descriptors with a null data address. Software can make
use of this property to cause the first condition under receive descriptor packing to
occur early. Hardware writes back null descriptors with the DD bit set in the status byte
and all other bits unchanged.
Null descriptor padding is not supported for packet split descriptors.
7.1.8
Receive Descriptor Queue Structure
Figure 30 shows the structure of the receive descriptor ring. Hardware maintains a
circular queue of descriptors and writes back used descriptors just prior to advancing
the head pointer. Head and tail pointers wrap back to base when size descriptors have
been processed.
Circular Buffer Queues
Base
Head
Receive
Queue
Tail
Base + Size
Figure 30. Receive Descriptor Ring Structure
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