82583V Datasheet, PDF (234/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.5.3
Flow Control Receive Threshold Low - FCRTL (0x02160; RW)
Note:
Note:
9.2.5.4
Field
Reserved
RTL
Reserved
XONE
Bit(s)
2:0
15:3
30:16
31
Initial
Value
0x0
0x0
0x0
0b
Description
Reserved
The underlying bits might not be implemented in all versions of the
chip. Must be written with 0x0.
Receive Threshold Low
FIFO low water mark for flow control transmission.
Reserved
Reads as 0x0. Should be written to 0x0 for future compatibility.
XON Enable
0b = Disabled.
1b = Enabled.
This register contains the receive threshold used to determine when to send an XON
packet. It counts in units of bytes. The lower 3 bits must be programmed to zero (8-
byte granularity). Software must set XONE to enable the transmission of XON frames.
Whenever hardware crosses the receive high threshold (becoming more full), and then
crosses the receive low threshold and XONE is enabled (= 1b), hardware transmits an
XON frame.
Note that flow control reception/transmission are negotiated capabilities by the auto-
negotiation process. When the device is manually configured, flow control operation is
determined by the RFCE and TFCE bits of the Device Control register.
This register's address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00168.
Flow Control Receive Threshold High - FCRTH (0x02168; RW)
Note:
Field
Reserved
RTH
Reserved
Bit(s)
2:0
15:3
31:16
Initial
Value
0x0
0x0
0x0
Description
Reserved
The underlying bits might not be implemented in all versions of the
chip. Must be written with 0x0.
Receive Threshold High
FIFO high water mark for flow control transmission.
Reserved
Reads as 0b. Should be written to 0b for future compatibility.
This register contains the receive threshold used to determine when to send an XOFF
packet. It counts in units of bytes. This value must be at least 8 bytes less than the
maximum number of bytes allocated to the Receive Packet Buffer (PBA.RXA), and the
lower 3 bits must be programmed to zero (8-byte granularity). Whenever the receive
FIFO reaches the fullness indicated by RTH, hardware transmits a pause frame if the
transmission of flow control frames is enabled.
Note that flow control reception/transmission are negotiated capabilities by the auto-
negotiation process. When the device is manually configured, flow control operation is
determined by the RFCE and TFCE bits of the Device Control register.
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