82583V Datasheet, PDF (103/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
1 Byte
S
Up to 6 Bytes Preamble...
1 Byte
6 Bytes
6 Bytes
SFD
Destination
Address
Source
Address
2 Bytes
Type/Length
2 Bytes
(min_FrameSize -160)/8
Bytes
MAC Control
Opcode
MAC Control
Parameters
4 Bytes
FCS
1 Byte
T
Figure 25.
802.3x MAC Control Frame Format
Where S is the start-of-packet delimiter and T is the first part of the end-of-packet
delimiters for 802.3z encapsulation.
The receiver is enabled to receive flow control frames if flow control is enabled via the
RFCE bit in the Device Control (CTRL) register.
Note:
Flow control capability must be negotiated between link partners via the auto-
negotiation process. The auto-negotiation process might modify the value of these bits
based on the resolved capability between the local device and the link partner.
Once the receiver validates receiving an XOFF or pause frame, the 82583V performs
the following:
• Increments the appropriate statistics register(s).
• Sets the TXOFF bit in the Device Status (STATUS) register.
• Initializes the pause timer based on the packet's Pause Timer field.
• Disables packet transmission or schedules the disabling of transmissions after the
current packet completes.
Resuming transmission can occur under the following conditions:
• An expired pause timer
• Receiving an XON frame (a frame with its pause timer set to zero)
Either condition clears the TXOFF status bit in the Device Status register and
transmission can resume. Note that hardware records the number of received XON
frames.
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