82583V Datasheet, PDF (26/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Electrical Specifications
3.3
3.4
Table 14.
Power Sequencing
For proper and safe operation, the power supplies must follow the following rule:
VDD3p3 (3.3 V dc) ≥ AVDD1p9 (1.9 V dc) ≥ VDD1p0 (1.05 V dc)
This means that VDD3p3 MUST start ramping before AVDD1p8 and VDD1p0, but
VDD1p0 MIGHT reach its nominal operating range before AVDD1p8 and VDD3p3.
Basically, the higher voltages must be greater than or equal to the lower voltages. This
is necessary to avoid low impedance paths through clamping diodes and to eliminate
back-powering.
The same requirements apply to the power-down sequence.
Internal Power On Reset must be low throughout the time that the power supplies are
ramping. This guarantees that the MAC and PHY resets cleanly. While Internal Power
On Reset is low, reset to the PHY is also asserted. After the power supplies are valid,
Internal
CLK125
Power On Reset must remain low
clock from the PHY is running.
for
at
least
t_CLK125START
to
guarantee
that
the
Power-On Reset
• Power up sequence – 3.3 V dc -> 1.9 V dc -> 1.05 V dc
• Power down sequence 1.05 V dc -> 1.9 V dc->3.3 V dc
Power Detection Thresholds
Symbol
Parameter
Specifications
Units
Min Typ Max
V1a
High threshold for 3.3 V dc supply
1.35 1.7
2.0
V dc
V2a
Low threshold for 3.3 V dc supply
1.35 1.6
1.9
V dc
V1b
High threshold for 1.05 V dc supply 0.6
0.7
0.75 V dc
V2b
Low threshold for 1.05 V dc supply 0.35 0.45 0.6
V dc
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