82583V Datasheet, PDF (215/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.2.24 EEPROM Write Register - EEWR (0x0102C; RW)
Note:
9.2.2.25
Field
START
DONE
ADDR
DATA
Bit(s)
0
1
15:2
31:16
Default
Description
Start Write
0b
Writing a 1b to this bit causes the 82583V to write a 16-bit word at
the address stored in the ADDR field in the external NVM. The data is
fetched from the DATA field. This bit is self-clearing.
Write Done
1b
Set to 1b when the write completes. Set to 0b when the write is in
progress. Writes by software are ignored.
Write Address
0x0
This field is written by software along with Start Write to indicate the
word address of the word to read.
0x0
Write Data
Data written to the NVM.
EEWR has direct access regardless of a valid signature in the NVM.
SW FLASH Burst Control Register - FLSWCTL (0x1030; RW)
Field
ADDR
CMD
CMDV
FLBUSY
Reserved
FLUDONE
DONE
WRDONE
Bit(s)
23:0
25:24
26
27
28
29
30
31
Default
Description
Address
0x0
This field is written by software along with Start Read or Start write to
indicate the Flash address to read or write.
Command
Indicates which command should be executed. Valid only when the
CMDV bit is set.
00b
00b = Reserved.
01b = DMA Write command (write up to 256 bytes).
10b = Reserved.
11b = Reserved.
Command Valid
0b
When set, indicates that software issues a new command.
Cleared by hardware at the end of the command.
Flash Busy
0b
This bit indicates that the Flash is busy processing a Flash transaction
and should not be accessed.
0b
Reserved
Flash Update Done
0b
This bit is set by the 82583V when it completes updating the Flash.
Software should clear it to zero before it updates the Flash.
Write Done
This bit clears after CMDV is set by software and is set back again
1b
when the Flash write transaction is done.
When writing a burst transaction the bit is cleared every time
software writes FLSWDATA.
Global Done
This bit clears after the CMDV bit is set by software and is set back
1b
again when the all Flash read/write transactions complete. For
example, the Flash unit finished to read/write all the requested read/
writes.
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