82583V Datasheet, PDF (225/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Note:
9.2.4.2
Field
Reserved
RxQ0
Reserved
TxQ0
Reserved
Other
Reserved
INT_
ASSERTED
Bit(s)
19:18
20
21
22
23
24
30:25
31
Initial
Value
00b
0b
0b
0b
0b
0b
0x0
0b
Description
Reserved
Receive Queue 0 Interrupt
Indicates Receive queue 0 write back or receive queue 0 descriptor
minimum threshold hit.
Reserved
Transmit Queue 0 Interrupt
Indicates transmit queue 0 write back.
Reserved
Other Interrupt. Indicates one of the following interrupts was set:
• Link Status Change.
• Receiver Overrun.
• MDIO Access Complete.
• Small Receive Packet Detected.
• Receive ACK Frame Detected.
Reserved
Reads as 0x0.
Interrupt Asserted
This bit is set when the LAN port has a pending interrupt. If the
interrupt is enabled in the PCI configuration space, an interrupt is
asserted.
This register contains all interrupt conditions for the 82583V. Whenever an interrupt
causing event occurs, the corresponding interrupt bit is set in this register. A PCIe
interrupt is generated whenever one of the bits in this register is set, and the
corresponding interrupt is enabled via the Interrupt Mask Set/Read register.
Whenever an interrupt causing event occurs, all timers of delayed interrupts are
cleared and their cause event is set in the ICR.
Reading from the ICR register has different effects according to the following three
cases:
• Case 1 - Interrupt Mask register equals 0x0000 (mask all): ICR content is cleared.
• Case 2 - Interrupt was asserted (ICR.INT_ASSERT=1) and auto mask is active: ICR
content is cleared, and the IAM register is written to the IMC register.
• Case 3 - Interrupt was not asserted (ICR.INT_ASSERT=0): Read has no side affect.
Writing a 1b to any bit in the register also clears that bit. Writing a 0b to any bit has no
effect on that bit.
The INT_ASSERTED bit is a special case. Writing a 1b or 0b to this bit has no affect. It
is cleared only when all interrupt sources are cleared.
Interrupt Throttling Register - ITR (0x000C4; R/W)
Field
INTERVAL
Reserved
Bit(s)
15:0
31:16
Initial
Value
0x0
0x0
Description
Minimum Inter-Interrupt Intervall
The interval is specified in 256 ns increments. Zero disables interrupt
throttling logic.
Reserved
Should be written with 0x0 to ensure future compatibility.
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