82583V Datasheet, PDF (114/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
7.0
7.1
7.1.1
Note:
Inline Functions
Packet Reception
Packet reception consists of recognizing the presence of a packet on the wire,
performing address filtering, storing the packet in the receive data FIFO, transferring
the data to the receive queue in host memory, and updating the state of a receive
descriptor.
Packet Address Filtering
Hardware stores incoming packets in host memory subject to the following filter
modes. If there is insufficient space in the receive FIFO, hardware drops them and
indicates the missed packet in the appropriate statistics registers.
The following filter modes are supported:
• Exact unicast/multicast
— The destination address must exactly match one of 16 stored addresses. These
addresses can be unicast or multicast.
The software device driver can only use 15 entries (entries 0-14).
• Promiscuous unicast
— Receive all unicasts
• Multicast
The upper bits of the incoming packet's destination address index is a bit vector that
indicates whether to accept the packet; if the bit in the vector is one, accept the
packet, otherwise, reject it. The 82583V provides a 4096-bit vector. Software provides
four choices of which bits are used for indexing. These are [47:36], [46:35], [45:34],
or [43:32] of the internally stored representation of the destination address (see
Figure 43)
• Promiscuous multicast
— Receive all multicast packets
• VLAN
Receive all VLAN packets that are for this station and have the appropriate bit set in the
VLAN filter table. A detailed discussion and explanation of VLAN packet filtering is
contained in section 7.5.3.
Normally, only good packets are received.
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