82583V Datasheet, PDF (287/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.8.22 Bias Setting Register 1 (Page 0), PHY Address 01; Register 29
9.2.8.23
Bits
Field
15:0 Bias setting1
Mode
R/W
HW Rst
SW Rst
Description
Retain
Used to optimize PHY performance in
1000Base-T mode. Set to 0x0003 when
initializing the 82583V to improve BER
performance.
Bias Setting Register 2 (Page 0), PHY Address 01; Register 30
9.2.8.24
Bits
Field
15:0 Bias setting2
Mode
R/W
HW Rst
SW Rst
Description
Retain
Used to optimize PHY performance in
1000Base-T mode. Set to 0x0000 when
initializing the 82583V to improve BER
performance.
MAC Specific Control Register 1 (Page 2), PHY Address 01; Register 16
Bits
Field
Mode HW Rst SW Rst
Description
15:14
Transmit
FIFO Depth
R/W
13:10 Reserved
R/W
9
Disable
fi_125_clk
R/W
8
Disable
fi_50_clk
R/W
7
Reserved
R/W
6:4
Reserved
R/W
GMII
3
Interface
Power
R/W
Down
2:0
Reserved
R/W
0x0
0x00
Retain
Retain
See
Description
Retain
See
Description
Retain
0x1
Update
0x0
Retain
0x1
Update
0x0
Retain
1000BASE-T:
00b = ± 16 bits.
01b = ± 24 bits.
10b = ± 32 bits.
11b = ± 40 bits.
Reserved, set to 0x00.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these registers
must be followed by a software reset to take effect.
After a hardware reset, this bit takes on the value of
pd_pwrdn_clk125_a. When pd_pwrdn_clk125_a
transitions from one to zero this bit is set to 0b. When
pd_pwrdn_clk125_a transitions from zero to one this
bit is set to 1b.
1b = fi_125_clk low.
0b = fi_125_clk toggle
After a hardware reset, this bit takes on the value of
pd_pwrdn_clk50_a. When pd_pwrdn_clk50_a
transitions from one to zero this bit is set to 0b. When
pd_pwrdn_clk50_a transitions from zero to one this
bit is set to 1b.
1b = fi_50_clk low.
0b = fi_50_clk toggle.
Reserved, write as 0x1.
Reserved, write as 0x00.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these registers
must be followed by a software reset to take effect.
This bit determines whether the GMII RX_CLK powers
down when register 0.11, 16_0.2 are used to power
down the 82583V or when the PHY enters the energy
detect state.
1b = Always power up.
0b = Can power down.
Reserved, write as 0x00.
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