82583V Datasheet, PDF (167/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
Note:
Table 44.
The Virtual LAN ID field indexes a 4096 bit vector. If the indexed bit in the vector is
one; there is a virtual LAN match. Software might set the entire bit vector to ones if the
node does not implement 802.1q filtering. The register description of the VLAN filter
table array is described in detail in section 9.2.5.20.
In summary, the 4096-bit vector is comprised of 128, 32-bit registers. Matching to this
bit vector follows the same algorithm as indicated in section 7.1.1 for multicast address
filtering. The VLAN Identifier (VID) field consists of 12 bits. The upper 7 bits of this field
are decoded to determine the 32-bit register in the VLAN filter table array to address
and the lower 5 bits determine which of the 32 bits in the register to evaluate for
matching.
Two other bits in the Receive Control register (see section 9.2.5.1), CFIEN and CFI, are
also used in conjunction with 802.1q VLAN filtering operations. CFIEN enables the
comparison of the value of the CFI bit in the 802.1q packet to the Receive Control
register CFI bit as acceptance criteria for the packet.
The VFE bit does not effect whether the VLAN tag is stripped. It only affects whether
the VLAN packet passes the receive filter.
Table 44 lists reception actions per control bit settings.
Packet Reception Decision Table
Is
packet
802.1q?
No
Yes
Yes
Yes
Yes
CTRL.
VME
X
0b
0b
1b
1b
RCTL.
VFE
X
0b
1b
0b
1b
Action
Normal packet reception.
Receive a VLAN packet if it passes the standard filters (only).
Leave the packet as received in the data buffer. VP bit in receive
descriptor is cleared.
Receive a VLAN packet if it passes the standard filters and the
VLAN filter table. Leave the packet as received in the data buffer
(for example, the VLAN tag would not be stripped). VP bit in
receive descriptor is cleared.
Receive a VLAN packet if it passes the standard filters (only). Strip
off the VLAN information (four bytes) from the incoming packet
and store in the descriptor. Sets the VP bit in receive descriptor.
Receive a VLAN packet if it passes the standard filters and the
VLAN filter table. Strip off the VLAN information (four bytes) from
the incoming packet and store in the descriptor. Sets the VP bit in
receive descriptor.
Note:
7.6
A packet is defined as a VLAN/802.1q packet if its type field matches the VET.
LEDs
The 82583V implements three output drivers intended for driving external LED circuits
per port. Each of the three LED outputs can be individually configured to select the
particular event, state, or activity, which is indicated on that output. In addition, each
LED can be individually configured for output polarity as well as for blinking versus non-
blinking (steady-state) indication.
The configuration for LED outputs is specified via the LEDCTL register. Furthermore, the
hardware-default configuration for all the LED outputs, can be specified via NVM fields,
thereby supporting LED displays configurable to a particular OEM preference.
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