82583V Datasheet, PDF (335/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Design Considerations—82583V GbE Controller
10/100 M agnetics
M odule with Com m on M ode
Choke in Both Rx and Tx
P a th s
M D I_PLU S (0)
58
M DI_M IN US (0)
57
M D I_PLU S (1)
55
M DI_M IN US (1)
54
L A N _ 1 .9 V
50 Ohm
R esistors
82583V
M D I_PLU S (2)
53
M DI_M IN US (2)
52
M D I_PLU S (3)
50
M DI_M IN US (3)
49
Figure 54. 82583V 10/100 Mb/s Magnetics Module Connections (With CMC)
11.5.5
Layout Considerations for the Ethernet Interface
These sections provide recommendations for performing printed circuit board layouts.
Good layout practices are essential to meet IEEE PHY conformance specifications and
EMI regulatory requirements.
Critical signal traces should be kept as short as possible to decrease the likelihood of
being affected by high frequency noise from other signals, including noise carried on
power and ground planes. Keeping the traces as short as possible can also reduce
capacitive loading.
Since the transmission line medium extends onto the printed circuit board, special
attention must be paid to layout and routing of the differential signal pairs.
Designing for 1000 BASE-T Gigabit operation is very similar to designing for 10 and 100
Mb/s. For the 82583V, system level tests should be performed at all three speeds.
11.5.5.1
Guidelines for Component Placement
Component placement can affect signal quality, emissions, and component operating
temperature This section provides guidelines for component placement.
Careful component placement can:
• Decrease potential problems directly related to electromagnetic interference (EMI),
which could cause failure to meet applicable government test specifications.
• Simplify the task of routing traces. To some extent, component orientation will
affect the complexity of trace routing. The overall objective is to minimize turns and
crossovers between traces.
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