82583V Datasheet, PDF (95/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.1.8.4
6.1.8.5
6.1.9
6.2
Note:
6.2.1
Reset
The PCIe PHY can initiate core reset to the 82583V. The reset can be caused by three
sources:
• Upstream move to hot reset - Inband Mechanism (LTSSM).
• Recovery failure (LTSSM returns to detect).
• Upstream component move to disable.
Scrambler Disable
The Scrambler/de-scrambler functionality in the 82583V can be eliminated by two
mechanisms:
• Upstream according to the PCIe specification.
• NVM bit.
Performance Monitoring
The 82583V incorporates PCIe performance monitoring counters to provide common
capabilities to evaluate performance. The 82583V implements four 32-bit counters to
correlate between concurrent measurements of events as well as the sample delay and
interval timers. The four 32-bit counters can also operate in a two 64-bit mode to count
long intervals or payloads.
The list of events supported by the 82583V and the counters control bits are described
in the memory register map.
Ethernet Interface
The 82583V MAC provides a complete CSMA/CD function, supporting IEEE 802.3
(10 Mb/s), 802.3u (100 Mb/s), 802.3z, and 802.3ab (1000 Mb/s) implementations. The
82583V performs all of the functions required for transmission, reception, and collision
handling called out in the standards.
The GMII/MII mode used to communicate between the MAC and the PHY supports
10/100/1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s,
and only full-duplex operation at 1000 Mb/s.
The 82583V MAC is optimized for full-duplex operation in 1000 Mb/s mode. Half-duplex
1000 Mb/s operation is not supported.
The PHY features 10/100/1000-BaseT signaling and is capable of performing intelligent
power-management based on both the system power-state and LAN energy-detection
(detection of unplugged cables). Power management includes the ability to shutdown
to an extremely low (powered-down) state when not needed as well as ability to auto-
negotiate to a lower-speed 10/100 Mb/s operation when the system is in low power-
states.
MAC/PHY GMII/MII Interface
The 82583V MAC and PHY communicate through an internal GMII/MII interface that
can be configured for either 1000 Mb/s operation (GMII) or 10/100 Mb/s (MII) mode of
operation. For proper network operation, both the MAC and PHY must be properly
configured (either explicitly via software or via hardware auto-negotiation) to identical
speed and duplex settings. All MAC configuration is performed using device control
registers mapped into system memory or I/O space; an internal MDIO/MDC interface,
accessible via software, is used to configure the PHY operation.
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