82583V Datasheet, PDF (238/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
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9.2.5.12
PTHRESH is used to control when a prefetch of descriptors are considered. This
threshold refers to the number of valid, unprocessed receive descriptors the chip has in
its on-chip buffer. If this number drops below PTHRESH, the algorithm considers pre-
fetching descriptors from host memory. This fetch does not happen however, unless
there are at least HTHRESH valid descriptors in host memory to fetch.
HTHRESH should be given a non-zero value whenever PTHRESH is used.
WTHRESH controls the write back of processed receive descriptors. This threshold
refers to the number of receive descriptors in the on-chip buffer which are ready to be
written back to host memory. In the absence of external events (explicit flushes), the
write back occurs only after at least WTHRESH descriptors are available for write back.
Possible values:
GRAN = 1b (descriptor granularity):
PTHRESH = 0..47
WTHRESH = 0..63
HTHRESH = 0..63
GRAN = 0 (cacheline granularity):
PTHRESH = 0..3 (for 16 descriptors cacheline - 256 bytes)
WTHRESH = 0..3
HTHRESH = 0..4
For any WTHRESH value other than zero - packet and absolute timers must get a non-
zero value for WTHRESH feature to take affect.
Since the default value for write-back threshold is one, the descriptors are normally
written back as soon as one cache line is available. WTHRESH must contain a non-zero
value to take advantage of the write-back bursting capabilities of the 82583V.
Receive Interrupt Absolute Delay Timer- RADV (0x0282C; RW)
Field
Delay
Reserved
Bit(s)
15:0
31:16
Initial
Value
0x0
0x0
Description
Receive absolute delay timer measured in increments of 1.024 μs (0=
disabled).
Reserved
Reads as 0x0.
If the packet delay timer is used to coalesce receive interrupts, it ensures that when
receive traffic abates, an interrupt is generated within a specified interval of no
receives. During times when receive traffic is continuous, it might be necessary to
ensure that no receive remains unnoticed for too long an interval. This register can be
used to ensure that a receive interrupt occurs at some predefined interval after the first
packet is received.
When this timer is enabled, a separate absolute count-down timer is initiated upon
successfully receiving each packet to system memory. When this absolute timer
expires, pending receive descriptor write backs are flushed and a receive timer
interrupt is generated.
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