82583V Datasheet, PDF (150/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
The TCP bit identifies the packet as either TCP or UDP (non-TCP). This affects the
processing of the header information.
7.2.9.7
Status - STA
Four bits are reserved to provide transmit status, although only one is currently
assigned for this specific descriptor type.
The status word will only be written back to host memory in cases where the RS bit is
set in the command. DD indicates that the descriptor is done and is written back after
the descriptor has been processed only if the RS bit was set.
3
2
1
0
Reserved
DD
Figure 36. Transmit Status Layout
Rsv (bits 3-1) - Reserved
DD (bit 0) - Descriptor Done
7.2.10 Extended Data Descriptor Format
63
0 _Addresses
8 _VLAN
48 47
40 39
36 35
32 31 24 23
20 19
0
POPTS
ExtCMD
STA
DCMD DTYP
DTALEN
Status
Command
15 13 12 11
07
21
0 3 1 03
10 7 6 5 4 3 2
1
0
PRI CFI VLAN ID RSV TXSM IXSM RSV TS RSV
DD IDE VLE DEXT RSV RS TSE IFCS EOP
Figure 37. Extended Data Descriptor Format
The extended data descriptor is the companion to the context descriptor described in
the previous section. This descriptor type points to the location of the data in the host
memory.
To select this descriptor format, bit 29 (TDESC.DEXT) must be set to 1b and
TDESC.DTYP must be set to 0x0001. In this case, the descriptor format is defined as
shown in Figure 37.
The first Qword of this descriptor type contains the address of a data buffer in host
memory. This buffer contains all or a portion of a transmit packet.
The second Qword of this descriptor contains information about the data pointed to by
this descriptor as well as descriptor processing options.
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