82583V Datasheet, PDF (172/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Power Management and Delivery
Internal Power
On Reset
assertion
Hot (in-band)
Reset
PE_RST_N de-
assertion and
EEPROM read
done
Dr
PE_RST_N
assertion
D0u
PE_RST_N
assertion
D3
Enable
master or
slave access
Write 00b
to power
state
PE_RST_N
assertion
Write 11b
to power
state
D0a
Figure 40. Power Management State Diagram
8.4.2
Auxiliary Power Usage
If ADVD3WUC=1b, the 82583V uses the AUX_PWR indication that auxiliary power is
available to the controller, and therefore advertises D3cold wake up support. The
amount of power required for the function (which includes the entire NIC) is advertised
in the Power Management Data register, which is loaded from the NVM.
If D3cold is supported, the PME_En and PME_Status bits of the Power Management
Control/Status Register (PMCSR), as well as their shadow bits in the Wake Up Control
(WUC) register is reset only by the power up reset (detection of power rising).
The only effect of setting AUX_PWR to 1b is advertising D3cold wake up support and
changing the reset function of PME_En and PME_Status. AUX_PWR is a strapping option
in the 82583V.
The 82583V tracks the PME_En bit of the Power Management Control / Status Register
(PMCSR) and the Auxiliary (AUX) Power PM Enable bit of the PCIe Device Control
register to determine the power it might consume (and therefore its power state) in the
D3cold state (internal Dr state).
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