82583V Datasheet, PDF (80/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.0
6.1
Interconnects
PCIe
PCIe is a third generation I/O architecture that enables cost competitive, next
generation I/O solutions providing industry leading price/performance and feature
richness. It is an industry-driven specification.
PCIe defines a basic set of requirements that comprehends the majority of the targeted
application classes. High-end application requirements such as Enterprise class servers
and high-end communication platforms are delivered by a set of advanced extensions
that compliment the baseline requirements.
To guarantee headroom for future applications of PCIe, a software-managed
mechanism for introducing new, enhanced capabilities in the platform is provided.
Figure 23 shows the PCIe architecture.
Config/OS
PCI.sys Compliant
S/W
Protocol
Preserve Driver Model
Advanced Xtensions
Common Base Protocol
Link
Configurable widths 1 .. 32
Figure 23.
Physical
(electrical
Mechanical)
Point to point, s2e.5r+iaGl, ^{bd/isfferential,}
hot-plug, inter-op formfactors
PCIe Stack Structure
The PCIe physical layer consists of a differential transmit pair and a differential receive
pair. Full-duplex data on these two point-to-point connections is self-clocked such that
no dedicated clock signals are required.
Note:
The bandwidth of this interface increases linearly with frequency.
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