82583V Datasheet, PDF (250/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
Note:
Note:
9.2.6.11
This feature operates by initiating a count-down timer upon successfully transmitting
the buffer. If a subsequent transmit delayed-interrupt is scheduled BEFORE the timer
expires, the timer is re-initialized to the programmed value and re-starts its count
down. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is generated.
Setting the value to 0b is not allowed. If an immediate (non-scheduled) interrupt is
desired for any transmit descriptor, the descriptor IDE should be set to 0b.
The occurrence of either an immediate (non-scheduled) or absolute transmit timer
interrupt halts the TIDV timer and eliminate any spurious second interrupts.
Transmit interrupts due to a Transmit Absolute Timer (TADV) expiration or an
immediate interrupt (RS=1b, IDE=0b) cancels a pending TIDV interrupt. The TIDV
countdown timer is re-loaded but halted, though it can be re-started by processing a
subsequent transmit descriptor.
This register’s address has been moved from where it was located in previous devices.
However, for backwards compatibility, this register can also be accessed at its alias
offset of 0x00440.
Writing this register with FPD set initiates an immediate expiration of the timer, causing
a write back of any consumed transmit descriptors pending write back, and results in a
transmit timer interrupt in the ICR.
FPD is self clearing.
Transmit Descriptor Control - TXDCTL (0x03828; RW)
Note:
Field
PTHRESH
Rsv
HTHRESH
Rsv
WTHRESH
Rsv
GRAN
LWTHRESH
Bit(s)
5:0
7:6
13:8
15:14
21:16
23:22
24
31:25
Initial
Value
0x0
0x0
0x0
0x0
0x0
0x0
0b
0x0
Description
Prefetch Threshold
Reserved
Host Threshold
Reserved
Write-Back Threshold
Reserved
Granularity
Units for the thresholds in this register.
0b = Cache lines
1b = Descriptors
Transmit Descriptor Low Threshold
Interrupt asserted when the number of descriptors pending service in
the transmit descriptor queue (processing distance from the TDT)
drops below this threshold.
This register controls the fetching and write back of transmit descriptors. The three
threshold values are used to determine when descriptors are read from and written to
host memory. The values can be in units of cache lines or descriptors (each descriptor
is 16 bytes) based on the GRAN flag.
When GRAN=1b all descriptors are written back (even if not requested).
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