82583V Datasheet, PDF (129/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
Note:
Note:
Software adds receive descriptors by advancing the tail pointer to refer to the address
of the entry just beyond the last valid descriptor. This is accomplished by writing the
descriptor tail register with the offset of the entry beyond the last valid descriptor. The
hardware adjusts its internal tail pointer accordingly. As packets arrive, they are stored
in memory and the head pointer is incremented by hardware. When the head pointer is
equal to the tail pointer, the queue is empty. Hardware stops storing packets in system
memory until software advances the tail pointer, making more receive buffers available.
The receive descriptor head and tail pointers reference 16-byte blocks of memory.
Shaded boxes in the figure represent descriptors that have stored incoming packets but
have not yet been recognized by software. Software can determine if a receive buffer is
valid by reading descriptors in memory rather than by I/O reads. Any descriptor with a
non-zero status byte has been processed by the hardware, and is ready to be handled
by the software.
When configured to work as a packet split feature, the descriptor tail needs to be
increment by software by two for every descriptor ready in memory (as the packet split
descriptors are 32 bytes while regular descriptors are 16 bytes).
The head pointer points to the next descriptor that will be written back. At the
completion of the descriptor write-back operation, this pointer is incremented by the
number of descriptors written back. Hardware OWNS all descriptors between [head...
tail]. Any descriptor not in this range is owned by software.
The receive descriptor ring is described by the following registers:
• Receive Descriptor Base Address registers (RDBA0)
— This register indicates the start of the descriptor ring buffer; this 64-bit address
is aligned on a 16-byte boundary and is stored in two consecutive 32-bit
registers. Hardware ignores the lower 4 bits.
• Receive Descriptor Length registers (RDLEN0)
— This register determines the number of bytes allocated to the circular buffer.
This value must be a multiple of 128 (the maximum cache line size). Since each
descriptor is 16 bytes in length, the total number of receive descriptors is
always a multiple of 8.
• Receive Descriptor Head register (RDH0)
— This register holds a value that is an offset from the base, and indicates the in-
progress descriptor. There can be up to 64 KB descriptors in the circular buffer.
Hardware maintains a shadow copy that includes those descriptors completed
but not yet stored in memory.
• Receive Descriptor Tail register (RDT0)
— This register holds a value that is an offset from the base, and identifies the
location beyond the last descriptor hardware can process. This is the location
where software writes the first new descriptor.
If software statically allocates buffers, and uses memory read to check for completed
descriptors, it simply has to zero the status byte in the descriptor to make it ready for
reuse by hardware. This is not a hardware requirement (moving the hardware tail
pointer is), but is necessary for performing an in-memory scan.
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