82583V Datasheet, PDF (5/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Datasheet—82583V GbE Controller
7.2 Packet Transmission ........................................................................................ 135
7.2.1 Transmit Functionality........................................................................... 135
7.2.2 Transmission Flow Using Simplified Legacy Descriptors.............................. 136
7.2.3 Transmission Process Flow Using Extended Descriptors.............................. 136
7.2.4 Transmit Descriptor Ring Structure ......................................................... 137
7.2.5 Overview of On-Chip Transmit Modes...................................................... 139
7.2.6 Pipelined Tx Data Read Requests ............................................................ 140
7.2.7 Transmit Interrupts .............................................................................. 141
7.2.8 Transmit Data Storage .......................................................................... 141
7.2.9 Transmit Descriptor Formats.................................................................. 142
7.2.10 Extended Data Descriptor Format ........................................................... 150
7.3 TCP Segmentation ........................................................................................... 154
7.3.1 TCP Segmentation Performance Advantages ............................................ 154
7.3.2 Ethernet Packet Format......................................................................... 154
7.3.3 TCP Segmentation Data Descriptors........................................................ 155
7.3.4 TCP Segmentation Source Data .............................................................. 156
7.3.5 Hardware Performed Updating for Each Frame ......................................... 156
7.3.6 TCP Segmentation Use of Multiple Data Descriptors .................................. 157
7.4 Interrupts ...................................................................................................... 160
7.4.1 Legacy and MSI Interrupt Modes ............................................................ 160
7.4.2 Registers............................................................................................. 160
7.4.3 Interrupt Moderation ............................................................................ 161
7.4.4 Clearing Interrupt Causes...................................................................... 164
7.5 802.1q VLAN Support ...................................................................................... 165
7.5.1 802.1q VLAN Packet Format .................................................................. 165
7.5.2 Transmitting and Receiving 802.1q Packets ............................................. 166
7.5.3 802.1q VLAN Packet Filtering ................................................................. 166
7.6 LEDs.............................................................................................................. 167
8.0 Power Management and Delivery........................................................................... 170
8.1 Assumptions................................................................................................... 170
8.2 Power Consumption ......................................................................................... 170
8.3 Power Delivery................................................................................................ 171
8.3.1 The 1.9 V dc Rail .................................................................................. 171
8.3.2 The 1.05 V dc Rail ................................................................................ 171
8.4 Power Management ......................................................................................... 171
8.4.1 82583V Power States............................................................................ 171
8.4.2 Auxiliary Power Usage........................................................................... 172
8.4.3 Power Limits by Certain Form Factors ..................................................... 173
8.4.4 Power States ....................................................................................... 173
8.4.5 Timing of Power-State Transitions .......................................................... 177
8.5 Wake Up ........................................................................................................ 180
8.5.1 Advanced Power Management Wake Up .................................................. 180
8.5.2 PCIe Power Management Wake Up.......................................................... 181
8.5.3 Wake-Up Packets ................................................................................. 181
9.0 Driver Programing Interface.................................................................................. 188
9.1 Introduction ................................................................................................... 188
9.1.1 Memory and I/O Address Decoding ......................................................... 188
9.1.2 Registers Byte Ordering ........................................................................ 191
9.1.3 Register Conventions ............................................................................ 191
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