82583V Datasheet, PDF (239/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.5.13
Setting this register to 0x0 disables the absolute timer mechanism (the RDTR register
should be used with a value of 0x0 to cause immediate interrupts for all receive
packets).
Receive interrupts due to a Receive Packet Timer (RDTR) expiration cancels a pending
RADV interrupt. If enabled, the RADV count-down timer is reloaded but halted, so as to
avoid generation of a serious second interrupt after the RDTR has been noted.
Receive Small Packet Detect Interrupt- RSRPD (0x02C00; R/W)
9.2.5.14
Field
SIZE
Reserved
Bit(s)
11:0
31:12
Initial
Value
0x0
X
Description
If the interrupt is enabled any received packet of size <= SIZE asserts
an interrupt. SIZE is specified in bytes and includes the headers and
the CRC. It does not include the VLAN header in size calculation if it is
stripped.
Reserved.
Receive ACK Interrupt Delay Register - RAID (0x02C08; RW)
9.2.5.15
Field
RSV
ACK_DELAY
Bit(s)
16:31
15:0
Initial
Value
0x0
0x0
Description
Reserved
ACK delay timer measured in increments of 1.024 μs. When the
receive ACK frame detect interrupt is enabled in the IMS register, ACK
packets being received uses a unique delay timer to generate an
interrupt. When an ACK is received, an absolute timer loads to the
value of ACK_DELAY. The interrupt signal is set only when the timer
expires. If another ACK packet is received while the timer is counting
down, the timer is not reloaded to ACK_DELAY.
If an immediate (non-scheduled) interrupt is desired for any received ACK frame, the
ACK_DELAY should be set to x00.
Receive Checksum Control - RXCSUM (0x05000; RW)
Field
PCSS
IPOFLD
TUOFLD
Reserved
CRCOFL
IPPCSE
PCSD
Reserved
Bit(s)
7:0
8
9
10
11
12
13
31:14
Initial
Value
0x0
1b
1b
0b
0b
0b
0b
0x0
Description
Packet Checksum Start
IP Checksum Offload Enable
TCP/UDP Checksum Offload Enable
Reserved
CRC32 Offload Enable
IP Payload Checksum Enable
Packet Checksum Disable
Reserved
The Receive Checksum Control register controls the receive checksum offloading
features of the 82583V. The 82583V supports the offloading of three receive checksum
calculations: the packet checksum, the IP header checksum, and the TCP/UDP
checksum.
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