82583V Datasheet, PDF (38/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Initialization
4.3
4.3.1
4. The following register fields do not follow the previously mentioned general rules:
— Packet Buffer Allocation (PBA) - reset on Internal Power On Reset only.
— Packet Buffer Size (PBS) - reset on Internal Power On Reset only.
— LED configuration registers.
— The Aux Power Detected bit in the PCIe Device Status register is reset on
Internal Power On Reset and PCIe Power Good only.
— FLA - reset on Internal Power On Reset only.
5. The NVM is loaded only when the LAN function exits D3hot state.
In situations where the device is reset using the software reset CTRL.RST, the TX data
lines will be forced to all zeros. This causes a substantial number of symbol errors to be
detected by the link partner.
Power Up
Power-Up Sequence
Figure 8 through Figure 14 shows the 82583V’s power-up sequencing.
Figure 8 shows a high-level view of the power sequence, while Figure 9 through
Figure 14 provides a more detailed description of each state.
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