82583V Datasheet, PDF (49/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Initialization—82583V GbE Controller
PCIe reference
clock
PERST#
NVM Load
PHY State
PCIe Link up
Wake
D-State
1 tclkpg
Active
L0
D0a
2
Any mode
3
tPWRGD-CLK
4
Active / Down
tee
Auto Ext.
Read Conf.
5
6
tpgtrn
tpgcfg
7
8
tpgres
9 10
L0
APM
Dr
D0u
D0a
Figure 18.
Table 22.
Global Reset Timing Diagram
Notes to Global Reset Timing Diagram
Note
1
2
3
4
5
6
7
8
9
10
The system must assert PE_RST_N before stopping the PCIe reference clock. It
must also wait tl2clk after link transition to L2/L3 before stopping the reference
clock.
On assertion of PE_RST_N, the 82583V transitions to Dr state and the PCIe link
transition to electrical idle. The PHY state is defined by the wake configuration.
The system starts the PCIe reference clock tPWRGD-CLK before de-assertion
PE_RST_N.
De-assertion of PE_RST_N causes the NVM to be re-read, asserts PHY power-
down, and disables wake up.
After reading the NVM base area, PHY reset is de-asserted. APM wake might be
enabled.
Link training starts after the NVM was fully read (including extended
configuration if needed).
Link training starts after tpgtrn from PE_RST_N de-assertion.
A first PCIe configuration access might arrive after tpgcfg from PE_RST_N de-
assertion.
A first PCI configuration response can be sent after tpgres from PE_RST_N de-
assertion.
Writing a 1b to the Memory Access Enable bit in the PCI Command register
transitions the device from D0u to D0 state.
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