82583V Datasheet, PDF (102/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.2.6
6.2.6.1
Note:
Flow Control
Flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow
control defined by 802.3z, are supported in the MAC. The following seven registers are
defined for the implementation of flow control:
• Flow Control Address Low (FCAL) - 6-byte flow control multicast address
• Flow Control Address High (FCAH) - 6-byte flow control multicast address
• Flow Control Type (FCT) - 16-bit field that indicates flow control type
• Flow Control Receive Thresh Hi (FCRTH) - 13-bit high-water mark indicating receive
buffer fullness
• Flow Control Receive Thresh Lo (FCRTL) - 13-bit low-water mark indicating receive
buffer emptiness
• Flow Control Transmit Timer Value (FCTTV) - 16-bit timer value to include in
transmitted pause frames
• Flow Control Refresh Threshold Value (FCRTV) - 16-bit pause refresh threshold
value
Flow control allows for local controlling of network congestion levels. Flow control is
implemented as a means of reducing the possibility of receive buffer overflows. Receive
buffer overflows result in the dropping of received packets. Flow control is
accomplished by notifying the transmitting station that the receiving station receive
buffer is nearly full.
Implementing asymmetric flow control allows for one link partner to send flow control
packets while being allowed to ignore their reception. For example, not required to
respond to pause frames.
MAC Control Frames and Reception of Flow Control Packets
Three comparisons are used to determine the validity of a flow control frame. All three
must be true for a positive result.
1. A match on the six-byte multicast address for MAC control frames or to the station
address of the device (Receive Address Register 0).
2. A match on the Type field.
3. A comparison of the MAC Control Opcode field.
The 802.3x standard defines the MAC control frame multicast address as 01-80-C2-00-
00-01. This address must be loaded into the Flow Control Address Low/High registers
(FCAL/FCAH).
The Flow Control Type (FCT) register contains a 16-bit field that is compared against
the flow control packet's Type field to determine if it is a valid flow control packet: XON
or XOFF. 802.3x reserves this as 0x8808. This value must be loaded into the Flow
Control Type register.
The final check for a valid pause frame is the MAC control opcode. At this time, only the
pause control frame opcode is defined. It has a value of 0x0001.
Frame-based flow control differentiates XOFF from XON based on the value of the
Pause Timer field. Non-zero values constitute XOFF frames while a value of zero
constitutes an XON frame. Values in the timer field are in units of slot time. A slot time
is hard wired to 64-byte times or 512 ns.
An XON frame signals the cancellation of the pause from being initiated by an XOFF
frame (pause for zero slot times).
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