82583V Datasheet, PDF (90/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.1.5.1.1
6.1.5.1.2
6.1.6
6.1.6.1
Completion Timeout Mechanism
In any split transaction protocol, there is a risk associated with the failure of a
requester to receive an expected completion. To enable requesters to attempt recovery
from this situation in a standard manner, the completion timeout mechanism is defined.
• The completion timeout mechanism is activated for each request that requires one
or more completions when the request is transmitted.
• The completion timeout timer should not expire in less than 10 ms.
• The completion timeout timer must expire if a request is not completed in 50 ms.
• A completion timeout is a reported error associated with the requestor device/
function.
A Memory Read Request for which there are multiple completions are considered
completed only when all completions are received by the requester. If some, but not all,
requested data is returned before the completion timeout timer expires, the requestor
is permitted to keep or discard the data that was returned prior to timer expiration.
Out of Order Completion Handling
In a split transaction protocol, when using multiple read requests in a multi processor
environment, there is a risk that the completions might arrive from the host memory
out of order and interleave. In this case the host interface role is to sort the request
completions and transfer them to the Ethernet core in the correct order.
Error Events and Error Reporting
Mechanism in General
PCIe defines two error reporting paradigms: the baseline capability and the Advanced
Error Reporting (AER) capability. The baseline error reporting capabilities are required
of all PCIe devices and define the minimum error reporting requirements. The AER
capability is defined for more robust error reporting and is implemented with a specific
PCIe capability structure.
Both mechanisms are supported by the 82583V.
Also the SERR# Enable and the Parity Error bits from the legacy command register take
part in the error reporting and logging mechanism.
Figure 24 shows, in detail, the flow of error reporting in the 82583V.
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