82583V Datasheet, PDF (308/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
10.1.2.15 Cap_Ptr (Offset 0x34)
The Capabilities Pointer field (Cap_Ptr) is an 8-bit field that provides an offset in the
device's PCI configuration space for the location of the first item in the capabilities
linked list. The 82583V sets this bit, and implements a capabilities list, to indicate that
it supports:
• PCI power management
• MSI
• PCIe extended capabilities
Its value, 0xC8, is the address of the first entry: PCI power management.
Address
0xC8-CF
0xD0-DF
0xA0-AB
0xE0-F3
Item
PCI power management
MSI
Reserved
PCIe Capabilities
Next Pointer
0xD0
0xE0
0x00
0xA0
10.1.2.16 Interrupt Line (Offset 0x3C)
Read/write register programmed by software to indicate which of the system interrupt
request lines this device's interrupt pin is bound to. See the PCI definition for more
details.
10.1.2.17 Interrupt Pin (Offset 0x3D)
Read-only register. The LAN implements legacy interrupt on INTA.
10.1.2.18 Max_Lat/Min_Gnt (Offset 0x3E)
Not used. Hardwired to 0b.
10.1.3
Table 53.
PCI Power Management Registers
All fields are reset on full power up. All of the fields except PME_En and PME_Status are
reset on exit from D3cold state.
See the detailed description for registers loaded from the NVM at initialization time.
Initialization values of the configuration registers are marked in parenthesis.
Some fields in this section depend on the Power Management Ena bits in the NVM word
0x0A.
Table 53 lists the organization of the PCI Power Management register block. Light-blue
fields are read only fields.
Power Management Register Block
Byte Offset
0xC8
0xCC
Byte 3
Byte 2
Byte 1
Byte 0
Power Management Capabilities (PMC)
Next Pointer
(0xD0)
Capability ID
(0x01)
Data
PMCSR_BSE Bridge Power Management Control / Status
Support Extensions Register (PMCSR)
308