82583V Datasheet, PDF (252/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
9.2.6.12 Transmit Absolute Interrupt Delay Value-TADV (0x0382C; RW)
9.2.7
Note:
Note:
Note:
Field
IDV
Reserved
Bit(s)
15:0
31:16
Initial
Value
0x0
0x0
Description
Interrupt Delay Value
Counts in units of 1.024 μs. (0b = disabled).
Reads as 0x0. Should be written to 0x0 for future compatibility.
The transmit interrupt delay timer (TIDV) can be used to coalesce transmit interrupts.
However, it might be necessary to ensure that no completed transmit remains
unnoticed for too long an interval in order to ensure timely release of transmit buffers.
This register can be used to ENSURE that a transmit interrupt occurs at some pre-
defined interval after a transmit completes. Like the delayed-transmit timer, the
absolute transmit timer ONLY applies to transmit descriptor operations where
1. Interrupt-based reporting is requested (RS set).
2. The use of the timer function is requested (IDE is set).
This feature operates by initiating a count-down timer upon successfully transmitting
the buffer. When the timer expires, a transmit-complete interrupt (ICR.TXDW) is
generated. The occurrence of either an immediate (non-scheduled) or delayed transmit
timer (TIDV) expiration interrupt halts the TADV timer and eliminates any spurious
second interrupts.
Setting the value to zero, disables the transmit absolute delay function. If an
immediate (non-scheduled) interrupt is desired for any transmit descriptor, the
descriptor IDE should be set to 0b.
Statistic Register Descriptions
All statistics registers reset when read. In addition, they stick at 0xFFFF_FFFF when the
maximum value is reached.
For the receive statistics it should be noted that a packet is indicated as received if it
passes the device’s filters and is placed into the packet buffer memory. A packet does
not have to be DMA’d to host memory in order to be counted as received.
Due to divergent paths between interrupt-generation and logging of relevant statistics
counts, it might be possible to generate an interrupt to the system for a noteworthy
event prior to the associated statistics count actually being incremented. This is
extremely unlikely due to expected delays associated with the system interrupt-
collection and ISR delay, but might be observed as an interrupt for which statistics
values do not quite make sense. Hardware guarantees that any event noteworthy of
inclusion in a statistics count is reflected in the appropriate count within 1 μs; a small
time-delay prior to read of statistics might be necessary to avoid the potential for
receiving an interrupt and observing an inconsistent statistics count as part of the ISR.
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