82583V Datasheet, PDF (306/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Programing Interface
10.1.2.10 Base Address Registers (Offset 0x10 - 0x27)
The Base Address Registers (BARs) are used to map the 82583V register space. The
82583V BARs are defined as non-prefetchable, and therefore support 32-bit addressing
only.
Note:
Note:
Note:
BAR
0
1
2
3
4
5
Addr.
0x10
0x14
0x18
0x1C
0x20
0x24
31
4
Memory BAR (R/W - 31:17; 0b - 16:4)
Flash BAR (R/W - 31:23/16; 0b - 22/15:4)
IO BAR (R/W - 31:5; 0b - 4:1)
Reserved (read as all 0b’s)
Reserved (read as all 0b’s)
Reserved (read as all 0b’s)
3
21
0
0b
00b
0b
0b
00b
0b
0b 1b
Flash size is defined by the NVM.
The default setting of the Flash BAR enables software implement initial programming of
empty (non-valid) Flash via the (parallel) Flash BAR.
The 82583V requests I/O resources to support pre-boot operation (prior to allocating
physical memory base addresses).
All BARs have the following fields:
Field
Mem
Mem Type
Prefetch
Mem
Memory
Address
Space
IO Address
Space
Bit(s)
0
2:1
3
31:4
31:2
R/W
R
R
R
R/W
R/W
Initial
Value
Description
0b for
memory
0b = Memory space
1b for I/O ^{1b = I/O space.}
00b (for
32-bit)
Indicates the address space size.
00b = 32-bit
10b = 64-bit
The 82583V BARs are 32-bit only.
0b = Non-prefetchable space.
0b
1b = Prefetchable space.
The 82583V implements non-prefetchable space since it has
read side effects.
Read/Write bits and hardwired to 0b depending on the
memory mapping window sizes:
LAN memory spaces are 128 KB.
0x0
LAN Flash spaces can be 64 KB and up to 4 MB in powers of
2.
Flash window size is set by the NVM. The Flash BAR can also
be disabled by the NVM.
Read/Write bits and hardwired to 0b depending on the I/O
0x0
mapping window sizes:
LAN I/O space is 32 bytes.
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