82583V Datasheet, PDF (86/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.1.3.8
6.1.3.8.1
6.1.3.8.2
6.1.3.8.3
Transaction Attributes
Traffic Class (TC) and Virtual Channels (VC)
The 82583V supports only TC = 0 and VC = 0 (default).
Relaxed Ordering
The 82583V takes advantage of the relaxed ordering rules in PCIe by setting the
relaxed ordering bit in the packet header. The 82583V also enables the system to
optimize performance in the following cases:
• Relaxed ordering for descriptor and data reads: When the 82583V is a master in a
read transaction, its split completion has no relationship with the writes from the
CPUs (same direction). It should be allowed to bypass the writes from the CPUs.
• Relaxed ordering for receiving data writes: When the 82583V masters receive data
writes, it also enables them to bypass each other in the path to system memory
because the software does not process this data until their associated descriptor
writes have been completed.
• The 82583V cannot perform relax ordering for descriptor writes or an MSI write.
Relaxed ordering can be used in conjunction with the no-snoop attribute to enable the
memory controller to advance non-snoop writes ahead of earlier snooped writes.
Relaxed ordering is enabled in the 82583V by setting the RO_DIS bit to 0b in the
CTRL_EXT register.
Snoop Not Required
The 82583V sets the Snoop Not Required attribute bit for master data writes. System
logic can provide a separate path into system memory for non-coherent traffic. The
non-coherent path to system memory provides higher, more uniform, bandwidth for
write requests.
The Snoop Not Required attribute bit does not alter transaction ordering. Therefore, to
achieve maximum benefit from snoop not required transactions, it is advisable to set
the relaxed ordering attribute as well (assuming that system logic supports both
attributes).
Software configures no-snoop support through the 82583V’s control register and a set
of NONSNOOP bits in the GCR register in the CSR space. The default value for all bits is
disabled.
The 82583V supports a No-Snoop bit for each relevant DMA client:
1. TXDSCR_NOSNOOP - Transmit descriptor read.
2. TXDSCW_NOSNOOP - Transmit descriptor write.
3. TXD_NOSNOOP - Transmit data read.
4. RXDSCR_NOSNOOP - Receive descriptor read.
5. RXDSCW_NOSNOOP - Receive descriptor write.
6. RXD_NOSNOOP - Receive data write.
All PCIe functions in the 82583V are controlled by this register.
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