82583V Datasheet, PDF (270/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Driver Programing Interface
Bits
Field
Mode
11
Power Down R/W
10
Isolate
RO
Restart
9
Copper
Auto-
R/W,SC
Negotiation
Copper
8
Duplex
Mode
R/W
7
Collision
Test
RO
Speed
6
Selection
R/W
(MSB)
5:0 Reserved
RO
HW Rst SW Rst
Description
See
Description
0x0
0x0
0x1
Retain
0x0
SC
Update
Power down is controlled via register 0.11 and
16_0.2. Both bits must be set to 0b before the PHY
transitions from power down to normal operation.
When the port is switched from power down to
normal operation, a software reset and restart
auto-negotiation are performed even when bits
Reset (0_15) and Restart Auto-Negotiation (0.9)
are not set by the user. IEEE power down shuts
down the 82583V except for the GMII interface if
16_2.3 is set to 1b. If 16_2.3 is set to 0b, then the
GMII interface also shuts down. After a hardware
reset, this bit takes on the value of pd_pwrdn_a.
1b = Power down.
0b = Normal operation.
When pd_pwrdn_a transitions from 1b to 0b this
bit is set to 0b. When pd_pwrdn_a transitions from
0b to 1b this bit is set to 1b.
This bit has no effect.
When pd_aneg_now_a transitions from 0b to 1b
this bit is set to 1b. Auto-negotiation automatically
restarts after hardware or software reset
regardless of whether or not the Restart bit (0.9) is
set.
1b = Restart auto-negotiation process.
0b = Normal operation.
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these
registers must be followed by a software reset to
take effect. A write to this register bit does not
take effect until any one of the following also
occurs:
• Software reset is asserted (register 0.15).
• Restart auto-negotiation is asserted (register
0.9).
• Power down (register 0.11, 16_0.2) transitions
from power down to normal operation.
1b = Full-duplex.
0b = Half-duplex.
0x0
0x0
This bit has no effect.
0x1
Update
Always 0x0
Always
0x0
Changes to this bit are disruptive to the normal
operation; therefore, any changes to these
registers must be followed by a software reset to
take effect. A write to this register bit does not
take effect until any one of the following occurs:
• Software reset is asserted (register 0.15).
• Restart auto-negotiation is asserted (register
0.9).
• Power down (register 0.11, 16_0.2) transitions
from power down to normal operation (bit 6,
13).
11b = Reserved.
10b = 1000 Mb/s.
01b = 100 Mb/s.
00b = 10 Mb/s.
Reserved, always 0x0.
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