82583V Datasheet, PDF (368/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Board Layout and Schematic Checklists
Section
Clock Source
(Oscillator
Option)
Clock Source
(Crystal Option)
NVM
10/100/
1000Base-T
Interface
Traces
Check Items
Use 25 MHz 50 ppm oscillator.
Use a local decoupling capacitor on the
oscillator power supply.
The signal from the oscillator must be AC
coupled into the 82583V.
The clock signal going into the 82583V should
have an amplitude between 1.2 V dc and
1.9 V dc.
Use 25 MHz 30 ppm accuracy @ 25 °C crystal.
Avoid components that introduce jitter.
Connect two load capacitors to crystal; one on
XTAL1 and one on XTAL2. Use 27 pF
capacitors as a starting point, but be prepared
to change the value based on testing.
Use 0.1 μF decoupling capacitor.
If SPI Flash is used, connect pin 38 (NVMT) to
ground through a 1 KΩ resistor. If an SPI
EEPROM is used, connect pin 38 (NVMT) to 3.3
V dc through a 1 KΩ resistor.
The NVM must be powered from auxiliary
power.
Check connections to NVM_CS_N, NVM_SK,
NVM_SI, NVM_SO.
Design traces for 100 Ω differential impedance
(± 20%)
Avoid highly resistive traces (for example,
avoid four mil traces longer than four inches)
If a LAN switch is used or the trace length
from the 82583V is greater than four inches.
It might be necessary to boost the voltage at
the center tap with a separate power supply to
optimize MDI performance.
Remarks
The oscillator needs to maintain 50 ppm under all
applicable temperature and voltage conditions. Avoid
PLL clock buffers. Clock buffers introduce additional
jitter. Broadband peak-to-peak jitter must be less than
200 ps.
The 82583V has internal circuitry to set the input
common mode voltage.
This can be achieved with a resistive divider network.
Parallel resonant crystals are required. The Cload
should be 18 pF. Specify Equivalent Series Resistance
(ESR) to be 50 Ω or less.
Capacitance affects accuracy of the frequency. Must be
matched to crystal specifications, including estimated
trace capacitance in calculation.
Use capacitors with low ESR (types C0G or NPO, for
example). Refer to the design considerations section of
the datasheet and the Intel Ethernet Controllers Timing
Device Selection Guide for more information.
Applies to EEPROM or Flash devices.
Ensure pull-ups are connected to auxiliary power.
The NVM is read when the system is powered on even
before main power is available.
Pins on the 82583V are connected to same named pins
on the NVM. (NVM_SI connects to SI on NVM.
NVM_SO connects to SO on NVM.)
Primary requirement for 10/100/1000 Mb/s Ethernet.
Paired 50 Ω traces do not make 100 Ω differential. An
impedance calculator can be used to verify this.
If trace length is a problem, use thicker board
dielectrics to allow wider traces. Thicker copper is even
better than wider traces.
The boosted center tap voltage is between 1.9 V dc and
2.65 V dc and consume up to 200 mA.
Consider using a second 82583V instead of a LAN
switch and long MDI traces. It is difficult to achieve
excellent performance with long traces and analog LAN
switches. An optimization effort is required to tune the
system, the center tap voltage, and magnetics
modules.
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