82583V Datasheet, PDF (303/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Programing Interface—82583V GbE Controller
10.1.2
Table 52.
Mandatory PCI Configuration Registers
The PCI configuration registers map is depicted below. See a detailed description for
registers loaded from the NVM at initialization time. Initialization values of the
configuration registers are marked in parenthesis. Color Notation in Figure 44:
Light Blue
Read-only fields
Dark Grey
Not used. Hardwired to zero.
Configuration registers are assigned one of the attributes described in Table 52.
R/W Attribute Table
R/W
Attribute
RO
RW
R/W1C
ROS
RWS
R/W1CS
HwInit
RsvdP
RsvdZ
Description
Read-only register: Register bits are read-only and cannot be altered by software.
Read-write register: Register bits are read-write and can be either set or reset.
Read-only status, Write-1-to-clear status register, Writing a 0b to R/W1C bits has no effect.
Read-only register with sticky bits: Register bits are read-only and cannot be altered by
software. Bits are not cleared by reset and can only be reset with the PWRGOOD signal.
Devices that consume AUX power are not allowed to reset sticky bits when AUX power
consumption (either via AUX power or PME Enable) is enabled.
Read-write register with sticky bits: Register bits are read-write and can be either set or reset
by software to the desired state. Bits are not cleared by reset and can only be reset with the
PWRGOOD signal. Devices that consume AUX power are not allowed to reset sticky bits when
AUX power consumption (either via AUX power or PME Enable) is enabled.
Read-only status, Write-1-to-clear status register with sticky bits: Register bits indicate status
when read, a set bit indicating a status event can be cleared by writing a 1b. Writing a 0b to R/
W1C bits has no effect. Bits are not cleared by reset and can only be reset with the PWRGOOD
signal. Devices that consume AUX power are not allowed to reset sticky bits when AUX power
consumption (either via AUX power or PME Enable) is enabled.
Hardware Initialized: Register bits are initialized by firmware or hardware mechanisms such as
pin strapping or serial NVM. Bits are read-only after initialization and can only be reset (for
write-once by firmware) with PWRGOOD signal.
Reserved and Preserved: Reserved for future R/W implementations; software must preserve
value read for writes to bits.
Reserved and Zero: Reserved for future R/W1C implementations; software must use 0b for
writes to bits.
Byte Offset
0x0
0x4
0x8
0xC
0x10
0x14
0x18
0x1C
0x20
0x24
Byte 3
Byte 2
Byte 1
Byte 0
Device ID
Vendor ID (0x8086)
Status Register (0x0010)
Command Register (0x0000)
Class Code (0x020000)
Revision ID (0x00)
BIST (0x00)
Header Type (0x00 |
0x80)
Latency Timer (0x00)
Cache Line Size
(0x10)
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
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