82583V Datasheet, PDF (111/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.3.8.3
Note:
6.3.8.4
6.3.8.5
Case 2 - The 82583V is connected to a physical Flash device:
1. The 82583V writes the data to the shadow RAM and sets the Done bit in the EEWR
register.
2. Update of the shadow RAM to the Flash device as described in section 6.3.6.
Flash Byte Program Flow
Software initiates a byte write cycle via the Flash BAR as follows:
1. Write access to the Flash must be first enabled in the FLEW field in the EEC register.
2. Poll the FLBUSY flag in the FLA register until cleared.
3. Write the data byte to the Flash through the Flash BAR.
4. Repeat the steps 2 and 3 if multiple bytes should be programmed.
5. Clear the write enable in the FLEW field in the EEC register to protect the Flash
device.
As a response, hardware executes the following steps for each write access:
1. Initiate autonomous write enable instruction.
2. Initiate the program instruction right after the enable instruction.
3. Poll the Flash status until programming completes.
4. Clear the FLBUSY bit in the FLA register.
This section explains only the actual programming of a single byte or multiple bytes.
Flash Erase Flow
Device Erase Flow:
Erase instructions flow by software is almost identical to the program flow:
1. Erase access to the Flash must be first enabled in the FLEW field in the EEC
register.
2. Poll the FLBUSY flag in the FLA register until cleared.
3. Set the Flash Erase bit (FL_ER) in the FLA register.
4. Clear the Erase enable in the FLEW field in the EEC register to protect the Flash
device.
Flash Burst Program Flow
The 82583V provides a burst engine that can be useful for initial programming of the
entire Flash image according to the following flow:
1. Set the ADDR field with the byte resolution address in the FLSWCTL register.
2. Set the CMD field to 01b, which is the DMA write setting in the FLSWCTL register.
3. Write the first 32 bits of data to the FLSWGDATA register.
4. Set the RDCNT field to the byte count number in the FLSWCNT register.
5. Set the CMDV field in the FLSWCTL register to start a DMA write.
6. Hardware starts accessing the SPI bus and begins writing the first 32 bits from the
FLSWDATA register.
7. Once hardware writes the 32-bit data to the Flash, the DONE bit in the FLSWCTL
register is set indicating the next 32 bits are required.
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