82583V Datasheet, PDF (213/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
9.2.2.17 Packet Buffer Allocation - PBA (0x01000; RW)
Note:
Note:
Note:
Note:
9.2.2.18
Field
RXA
TXA
Bit(s)
15:0
31:16
Initial
Value
0x0014
0x0014
Description
Receive packet buffer allocation in KB. Upper 10 bits are read only as
0x0. Default is 20 KB.
Transmit packet buffer allocation in KB. These bits are read only.
Default is 20 KB.
This register sets the on-chip receive and transmit storage allocation ratio. The receive
allocation value is read/write for the lower 6 bits. The transmit allocation is read only
and is calculated based on RXA. The partitioning size is 1 KB.
Programming this register does not automatically re-load or initialize internal packet-
buffer RAM pointers. Software must reset both transmit and receive operation (using
the global device reset CTRL.RST bit) after changing this register in order for it to take
effect. The PBA register itself is not reset by asserting the global reset, but is only reset
upon initial hardware power on.
For best performance the transmit buffer allocation should be set to accept two full
sized packets.
Transmit packet buffer size should be configured to be more than 4 KB.
The 82583V supports a maximum frame size of 1514 bytes.
EEPROM Control Register - EECTL (0x1010; RO)
Note:
Field
Bit(s)
ADDR
14:0
START
15
WRITE
16
EEBUSY
17
Reserved
18
EE_TRANS_E 19
Reserved
31:20
Initial
Value
0x0
0b
0b
0b
0b
0b
0x0
Description
Address
This field is written by Start Read or Start write to indicate the
EEPROM word address to read or write.
Start
Writing a 1b to this bit causes the EEPROM to start the read or write
operation according to the write bit.
Write
This bit tells the EEPROM if the current operation is read or write.
0b = Read.
1b = Write.
EPROM Busy
This bit indicates that the EEPROM is busy doing an auto read.
Reserved
Transaction
This bit indicates that the register is in the middle of a transaction.
Reserved
This register is read/write by firmware and read only by software.
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