82583V Datasheet, PDF (4/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Datasheet
4.6 Software Initialization Sequence ..........................................................................51
4.6.1 Interrupts During Initialization..................................................................51
4.6.2 Global Reset and General Configuration .....................................................51
4.6.3 Link Setup Mechanisms and Control/Status Bit Summary .............................52
4.6.4 Initialization of Statistics..........................................................................53
4.6.5 Receive Initialization ...............................................................................54
4.6.6 Transmit Initialization..............................................................................54
5.0 Non-Volatile Memory (NVM) Map .............................................................................56
5.1 Basic Configuration Table....................................................................................56
5.1.1 Hardware Accessed Words .......................................................................58
5.1.2 Software Accessed Words ........................................................................72
6.0 Interconnects ..........................................................................................................80
6.1 PCIe ................................................................................................................80
6.1.1 Architecture, Transaction, and Link Layer Properties ....................................81
6.1.2 General Functionality ..............................................................................82
6.1.3 Transaction Layer ...................................................................................82
6.1.4 Flow Control...........................................................................................87
6.1.5 Host I/F.................................................................................................89
6.1.6 Error Events and Error Reporting ..............................................................90
6.1.7 Link Layer..............................................................................................93
6.1.8 PHY ......................................................................................................94
6.1.9 Performance Monitoring ...........................................................................95
6.2 Ethernet Interface .............................................................................................95
6.2.1 MAC/PHY GMII/MII Interface ....................................................................95
6.2.2 Duplex Operation for Copper PHY/GMII/MII Operation .................................96
6.2.3 Auto-Negotiation & Link Setup Features .....................................................97
6.2.4 Loss of Signal/Link Status Indication ....................................................... 100
6.2.5 10/100 Mb/s Specific Performance Enhancements ..................................... 101
6.2.6 Flow Control......................................................................................... 102
6.3 SPI Non-Volatile Memory Interface..................................................................... 105
6.3.1 General Overview ................................................................................. 105
6.3.2 Supported NVM Devices......................................................................... 105
6.3.3 NVM Device Detection ........................................................................... 106
6.3.4 Device Operation with an External EEPROM .............................................. 107
6.3.5 Device Operation with Flash ................................................................... 107
6.3.6 Shadow RAM ........................................................................................ 107
6.3.7 NVM Clients and Interfaces .................................................................... 109
6.3.8 NVM Write and Erase Sequence .............................................................. 110
7.0 Inline Functions ..................................................................................................... 114
7.1 Packet Reception ............................................................................................. 114
7.1.1 Packet Address Filtering......................................................................... 114
7.1.2 Receive Data Storage ............................................................................ 115
7.1.3 Legacy Receive Descriptor Format........................................................... 115
7.1.4 Extended Rx Descriptor ......................................................................... 118
7.1.5 Packet Split Receive Descriptor............................................................... 123
7.1.6 Receive Descriptor Fetching ................................................................... 127
7.1.7 Receive Descriptor Write Back ................................................................ 127
7.1.8 Receive Descriptor Queue Structure ........................................................ 128
7.1.9 Receive Interrupts ................................................................................ 130
7.1.10 Receive Packet Checksum Offloading ....................................................... 133
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