82583V Datasheet, PDF (104/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.2.6.2
6.2.6.3
Note:
Note:
Note:
Discard Pause Frames and Pass MAC Control Frames
Two bits in the Receive Control register are implemented specifically for control over
receipt of pause and MAC control frames. These bits are Discard PAUSE Frames (DPF)
and Pass MAC Control Frames (PMCF). See section 9.2.6.2 for DPF and PMCF bit
definitions.
The DPF bit forces the discarding of any valid pause frame addressed to the 82583V's
station address. If the packet is a valid pause frame and is addressed to the station
address (receive address [0]), the 82583V does not pass the packet to host memory if
the DPF bit is set to logic high. However, if a flow control packet is sent to the station
address and is a valid flow control frame, it is then be transferred when DPF is set to
0b. This bit has no affect on pause operation, only the DMA function.
The PMCF bit enables for the passing of any valid MAC control frames to the system,
which does not have a valid pause opcode. In other words, the frame must have the
correct MAC control frame multicast address (or the MAC station address) as well as
the correct Type field match with the FCT register, but does not have the defined pause
opcode of 0x0001. Frames of this type are transferred to host memory when PMCF is a
logic high.
Transmitting PAUSE Frames
Transmitting pause frames is enabled by software by writing a 1b to the TFCE bit in the
Device Control register.
Similar to receiving flow control packets, XOFF packets can be transmitted only if this
configuration has been negotiated between the link partners via the auto-negotiation
process. In other words, setting this bit indicates the desired configuration. Resolving
the auto-negotiation process is described in section 6.2.3.
The content of the Flow Control Receive Threshold High register determines at what
point hardware transmits a pause frame. Hardware monitors the fullness of the receive
FIFO and compares it with the contents of FCRTH. When the threshold is reached,
hardware sends a pause frame with its pause time field equal to FCTTV.
At the time threshold is reached, the hardware starts counting an internal shadow
counter FCRTV (reflecting the pause time-out counter at the partner end) from zero.
When the counter reaches the value indicated in the FCRTV register, then, if the pause
condition is still valid (meaning that the buffer fullness is still above the low
watermark), an XOFF message is sent again and the shadow counter starts counting
again.
Once the receive buffer fullness reaches the low water mark, hardware sends an XON
message (a pause frame with a timer value of zero). Software enables this capability
with the XONE field of the FCRTL.
Hardware sends one more pause frame if it has previously sent one and the FIFO
overflows (so the threshold must not be set greater than the FIFO size). This is
intended to minimize the amount of packets dropped if the first pause frame does not
reach its target. Since the secure receive packets use the same data path, the behavior
is identical when secure packets are received.
Transmitting flow control frames should only be enabled in full-duplex mode per the
IEEE 802.3 standard. Software should ensure that transmitting flow control packets is
disabled when the 82583V is operating in half-duplex mode.
Regardless of the mechanism above, each time a receive packet is dropped due to lack
of space in the internal receive buffer, a pause frame is transmitted as well (if TFCE bit
in the Device Control register is enabled).
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