82583V Datasheet, PDF (151/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
7.2.10.1
Data Length - DTALEN
The Data Length field (TDESC.DTALEN) is the total length of the data pointed to by this
descriptor (the entire send), in bytes. For data descriptors not associated with a TCP
segmentation operation (TDESC.TSE not set), the descriptor lengths are subject to the
same restrictions specified for legacy descriptors (the sum of the lengths of the data
descriptors comprising a single packet must be at least 80 bytes less than the allocated
size of the transmit FIFO).
7.2.10.2
Descriptor Type - DTYP
Setting the descriptor type (TDESC.DTYP) field to 0x0001 identifies this descriptor as
an extended data descriptor.
7.2.10.3
Table 42.
Command - DCMD
The command field (TDESC.DCMD) provides options that control the checksum
offloading TCP segmentation features, along with some of the generic descriptor
processing features. Table 42 lists the bit definitions for the DCMD field.
Command DCMD Fields
7
6
5
4
3
IDE
VLE
DEXT
RSV
RS
2
1
0
TSE
IFCS
EOP
IDE (bit 7) - Interrupt delay enable
VLE (bit 6) - VLAN enable
DEXT (bit 5) - Descriptor extension (must be 1b for this descriptor type)
RSV (bit 4) - Reserved
RS (bit 3) - Report status
TSE (bit 2) - TCP segmentation enable
IFCS (bit 1) - Insert FCS (also controls insertion of Ethernet CRC)
EOP (bit 0) - End of packet
IDE activates a transmit interrupt delay timer. Hardware loads a countdown register
when it writes back a transmit descriptor that has RS and IDE set. The value loaded
comes from the IDV field of the Interrupt Delay (TIDV) register. When the count
reaches zero, a transmit interrupt occurs if transmit descriptor write-back interrupts
(TXDW) are enabled. Hardware always loads the transmit interrupt counter whenever it
processes a descriptor with IDE set even if it is already counting down due to a
previous descriptor. If hardware encounters a descriptor that has RS set, but not IDE, it
generates an interrupt immediately after writing back the descriptor and clears the
interrupt delay timer. Setting the IDE bit has no meaning without setting the RS bit.
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