82583V Datasheet, PDF (137/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Inline Functions—82583V GbE Controller
7.2.4
• Software places the rest of the data to be transmitted in the host memory indicated
to the hardware by additional data descriptors.
• Hardware splits the data into multiple packets according to the Maximum Segment
Size (MSS) defined in the context descriptor. Hardware uses the prototype header
for each packet while it auto-updates some of the fields in the IP and TCP headers.
See more details in section 7.3.6.2.
• For each packet, the proceeding steps are the same as the legacy Tx descriptors as
previously described (starting at step number 4).
Transmit Descriptor Ring Structure
The transmit descriptor ring is described by the following registers:
• Transmit Descriptor Base Address register (TDBA)
— This register indicates the start address of the descriptor ring buffer in the host
memory; this 64-bit address is aligned on a 16-byte boundary and is stored in
two consecutive 32-bit registers. Hardware ignores the lower four bits.
• Transmit Descriptor Length register (TDLEN)
— This register determines the number of bytes allocated to the circular ring. This
value must be aligned to 128 bytes.
• Transmit Descriptor Head register (TDH)
— This register holds an index value that indicates the in-progress descriptor.
There can be up to 64 KB descriptors in the circular buffer. Reading this register
returns the value of head corresponding to descriptors already loaded in the
transmit FIFO.
• Transmit Descriptor Tail register (TDT)
— This register holds a value, which is an offset from the base (TDBA), and
indicates the location beyond the last descriptor hardware can process. This is
the location where software writes the next new descriptor.
Base +
TDLEN
Base
TDBA
Base+1
Head
TDH
Tail
TDT
Figure 33. Transmit Descriptor Ring Structure
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