82583V Datasheet, PDF (207/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Driver Programing Interface—82583V GbE Controller
Note:
a. Ready = 0b.
b. Interrupt Enable bit set to 1b or 0b.
c. Op-Code = 10b (read).
d. PHYADD = PHY address from the MDI register.
e. REGADD = Register address of the specific register to be accessed (0 through
31).
2. The MAC applies the following sequence on the MDIO signal to the PHY:
<PREAMBLE><01><10><PHYADD><REGADD><Z> where the Z stands for the
MAC tri-stating the MDIO signal.
3. The PHY returns the following sequence on the MDIO signal: <0><DATA><IDLE>.
4. The MAC discards the leading bit and places the following 16 data bits in the MII
register.
5. The 82583V asserts an interrupt indicating MDI done if the Interrupt Enable bit was
set.
6. The 82583V sets the Ready bit in the MII register indicating the read is complete.
7. The CPU might read the data from the MII register and issue a new MDI command.
For an MDI write cycle, the sequence of events is as follows:
1. The CPU performs a PCIe write cycle to the MII register with:
a. Ready = 0b.
b. Interrupt Enable bit set to 1b or 0b.
c. Op-Code = 01b (write).
d. PHYADD = PHY address from the MDI register.
e. REGADD = Register address of the specific register to be accessed (0 through
31).
f. Data = Specific data for desired control of the PHY.
2. The MAC applies the following sequence on the MDIO signal to the PHY:
<PREAMBLE><01><01><PHYADD><REGADD><10><DATA><IDLE>.
3. The 82583V asserts an interrupt indicating MDI done if the Interrupt Enable bit was
set.
4. The 82583V sets the Ready bit in the MII register to indicate step 2 has been
completed.
5. The CPU might issue a new MDI command.
An MDI read or write might take as long as 64 μs from the CPU write to the Ready bit
assertion.
If an invalid op-code is written by software, the MAC does not execute any accesses to
the PHY registers.
If the PHY does not generate a zero as the second bit of the turn-around cycle for
reads, the MAC aborts the access, sets the E (error) bit, writes 0xFFFF to the data field
to indicate an error condition, and sets the Ready bit.
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