82583V Datasheet, PDF (140/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Inline Functions
Note:
7.2.6
Note:
The device automatically selects the appropriate mode to use based on the current
packet transmission: legacy, extended, or segmentation.
While the architecture supports arbitrary ordering rules for the various descriptors,
there are restrictions including:
— Context descriptors should not occur in the middle of a packet or of a
segmentation.
— Data descriptors of different packet types (legacy, extended, or segmentation)
should not be intermingled except at the packet (or segmentation) level.
There are dedicated resources on-chip for both the extended and segmentation modes.
These modes remain constant until they are modified by another context descriptor.
This means that a set of configurations relevant to one mode can (and will) be used for
multiple packets unless a new mode is loaded prior to sending a new packet.
Pipelined Tx Data Read Requests
Transmit data request pipelining is the process by which a request for transmit data is
sent to the host memory before the read DMA request of the previously requested data
completes. Transmit pipeline requests is enabled using the MULR bit in the Transmit
Control (TCTL) register, Its initial value is loaded from the NVM.
The 82583V supports four pipelined requests from the Tx data DMA. In general, the
four requests can belong to the same packet or to consecutive packets. However, the
following restrictions apply:
• All requests for a packet are issued before a request is issued for a following
packet.
• If a request (for the following packet) requires context change, the request for the
following packet is not issued until the previous request is completed (such as, no
pipeline across contexts).
The PCIe specification does not ensure that completions for separate requests return in
order. The 82583V can handle completions that arrive in any order.
The 82583V incorporates a 2 KB buffer to support re-ordering of completions for the
four requests. Each request/completion can be up to 512 bytes long. The maximum
size of a read request is defined as follows:
• When the MULR bit is cleared, maximum request size in bytes is the min{2K,
Max_Read_Request_Size}
• When the MULR bit is set, maximum request size in bytes is the min{512,
Max_Read_Request_Size}
In addition to the four pipeline requests from the Tx data DMA, the 82583V can issue a
single read request from each of the 2 Tx descriptor and 2 Rx descriptor DMA engines.
The requests from the three sources (Tx data, Tx descriptor and Rx descriptor) are
independently issued. Each descriptor read request can fetch up to 16 descriptors
(equal to 256 bytes of data).
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