82583V Datasheet, PDF (309/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Programing Interface—82583V GbE Controller
10.1.3.1
10.1.3.2
10.1.3.3
The following section describes the register definitions, whether they are required or
optional for compliance, and how they are implemented in the 82583V.
Capability ID, Offset 0xC8, (RO)
This field equals 0x01 indicating the linked list item is the PCI Power Management
registers.
Next Pointer, Offset 0xC9, (RO)
This field provides an offset to the next capability item in the capability list. Its value of
0xD0 points to the MSI capability.
Power Management Capabilities (PMC), Offset 0xCA, (RO)
This field describes the device functionality at the power management states as
described in the following table.
Figure 45.
Bits
Default
R/W
Description
See value in
15:11 description
RO
column
10
0b
RO
9
0b
RO
8:6
000b
RO
5
1b
RO
4
0b
RO
3
0b
RO
2:0
010b
RO
PME_Support
This five-bit field indicates the power states in which the function might
assert PME# depending on NVM settings:
00000b = If PM is disabled in NVM (word 0x0A) than No PME support at
all states.
01001b = If PM is enabled in NVM and no Aux_Pwr than PME is
supported at D0 and D3_hot.
11001b = If PM is Enabled in NVM and Aux_Pwr, then PME is supported
at D0, D3_hot and D3_cold.
D2_Support
The 82583V does not support D2 state
D1_Support
The 82583V does not support D1 state
AUX Current
Required current defined in the Data register
DSI
The 82583V requires its software device driver to be executed following
transition to the D0 un-initialized state.
Reserved
PME_Clock
Disabled. Hardwired to 0b.
Version
The 82583V complies with PCI PM spec revision 1.1.
Power Management Capabilities (PMC)
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