82583V Datasheet, PDF (100/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

82583V GbE Controller—Interconnects
6.2.3.1.3
6.2.3.1.4
6.2.3.1.5
6.2.4
When MAC speed is neither forced nor auto-sensed by the MAC, the current MAC speed
setting and the speed indicated by the PHY is reflected in the Device Status register bits
STATUS.SPEED.
MAC Full/Half Duplex Resolution
The duplex configuration of the link is also resolved by the PHY during the auto-
negotiation process. The 82583V PHY provides an internal indication to the MAC of the
resolved duplex configuration using an internal full-duplex indication (FDX).
This internal duplex indication is normally sampled by the MAC each time the PHY
indicates the establishment of a good link (LINK indication). The PHY's indicated duplex
configuration is applied in the MAC and reflected in the MAC Device Status register
(STATUS.FD).
Software can override the duplex setting of the MAC via the CTRL.FD bit when the
CTRL.FRCDPLX (force duplex) bit is set. If CTRL.FRCDPLX is 0b, the CTRL.FD bit is
ignored and the PHY's internal duplex indication applied.
Using PHY Registers
The software device driver might be required under some circumstances to read from
or write to the MII management registers in the PHY. These accesses are performed via
the MDIC registers (see section 9.2.2.7). The MII registers enable the software device
driver to have direct control over the PHY's operation, which might include:
• Resetting the PHY
• Setting preferred link configuration for advertisement during the auto-negotiation
process
• Restarting the auto-negotiation process
• Reading auto-negotiation status from the PHY
• Forcing the PHY to a specific link configuration
The set of PHY management registers required for all PHY devices can be found in the
IEEE P802.3ab draft standard. The registers for the 82583V PHY are described in
section 9.2.
Comments Regarding Forcing Link
Forcing link requires the software device driver to configure both the MAC and PHY in a
consistent manner with respect to each other. After initialization, the software device
driver configures the desired modes in the MAC, then accesses the PHY registers to set
the PHY to the same configuration.
Before enabling the link, the speed and duplex settings of the MAC can be forced by
software using the CTRL.FRCSPD, CTRL.FRCDPX, CTRL.SPEED, and CTRL.FD bits. After
the PHY and MAC have both been configured, the software device driver should write a
1b to the CTRL.SLU bit.
Loss of Signal/Link Status Indication
PHY LOS/LINK signal provides an indication of physical link status to the MAC. This
signal from the PHY indicates whether the link is up or down; typically indicated after
successful auto-negotiation. Assuming that the MAC is configured with CTRL.SLU = 1b,
the MAC status bit STATUS.LU when read, generally reflects whether the PHY has link
(except under forced-link setup where even the PHY link indication might have been
forced).
100