82583V Datasheet, PDF (101/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Interconnects—82583V GbE Controller
6.2.5
6.2.5.1
Note:
When the link indication from the PHY is de-asserted, the MAC considers this to be a
transition to a link-down situation (such as, cable unplugged, loss of link partner, etc.).
If the LSC (Link Status Change) interrupt is enabled, the MAC generates an interrupt to
be serviced by the software device driver. See section 7.4 and section 9.2.4 for more
details.
10/100 Mb/s Specific Performance Enhancements
Adaptive IFS
The 82583V supports back-to-back transmit Inter-Frame-Spacing (IFS) of 960 ns in
100 Mb/s operation and 9.6 μs in 10 Mb/s operation. Although back-to-back
transmission is normally desirable, sometimes it can actually hurt performance in half-
duplex environments due to excessive collisions. Excessive collisions are likely to occur
in environments where one station is attempting to send large frames back-to-back,
while another station is attempting to send acknowledge (ACK) packets.
The 82583V contains an Adaptive IFS register (see section 9.2.6.3) that enables the
implementation of a driver-based adaptive IFS algorithm for collision reduction, which
is similar to Intel's other Ethernet products (such as PRO/100 adapters). Adaptive IFS
throttles back-to-back transmissions in the transmit MAC and delays their transfer to
the CSMA/CD transmit function and then can be used to delay the transmission of
back-to-back packets on the wire. Normally, this register should be set to zero.
However, if additional delay is desired between back-to-back transmits, then this
register can be set with a value greater than zero. This can be helpful in high-collision
half-duplex environments.
The AIFS field provides a similar function to the IGPT field in the TIPG register (see
section 9.2.6.3). However, this Adaptive IFS throttle register counts in units of GTX/
MTX_CLK clocks, which are 800 ns, 80 ns, 8 ns for 10/100/1000 Mb/s mode
respectively, and is 16 bits wide, thus providing a greater maximum delay value.
Using values lower than a certain minimum (determined by the ratio of GTX/MTX_CLK
clock to link speed), has no effect on back-to-back transmission. This is because the
82583V does not start transmission until the minimum IEEE IFS (9.6 μs at 10 Mb/s,
960 ns at 100 Mb/s, and 96 ns at 1000 Mb/s) has been met regardless of the value of
Adaptive IFS. For example, if the 82583V is configured for 100 Mb/s operation, the
minimum IEEE IFS at 100 Mb/s is 960 ns. Setting AIFS to a value of 10 (decimal) would
not effect back-to-back transmission time on the wire because the 800 ns delay
introduced (10 * 80 ns = 800 ns) is less than the minimum IEEE IFS delay of 960 ns.
However, setting this register with a value of 20 (decimal), which corresponds to
1600 ns for the above example, would delay back-to-back transmits because the
ensuing 1600 ns delay is greater than the minimum IFS time of 960 ns.
It is important to note that this register has no effect on transmissions that occur
immediately after receives or on transmissions that are not back-to-back (unlike the
IPGR1 and IPGR2 values in the TIPG register (see section 9.2.6.2). In addition,
Adaptive IFS also has no effect on re-transmission timing (re-transmissions occur after
collisions). Therefore, AIFS is only enabled in back-to-back transmission.
The AIFS value is not additive to the TIPG.IPGT value; instead, the actual IPG equals
the larger of the two, AIFS and TIPG.IPGT.
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