82583V Datasheet, PDF (313/374 Pages) Intel Corporation – Intel® 82583V GbE Controller

Programing Interface—82583V GbE Controller
10.1.5.1
Table 54.
PCIe Capability Structure
The 82583V implements the PCIe capability structure for end-point devices as listed in
Table 54.
PCIe Configuration Registers
Byte Offset
0xE0
0xE4
0xE8
0xEC
0xF0
Byte 3
Byte 2
Byte 1
Byte 0
PCIe Capability Register
Device Status
Link Status
Next Pointer
Capability ID
Device Capability
Device Control
Link Capability
Link Control
10.1.5.1.1
Capability ID, Offset 0xE0, (RO)
This field equals 0x10 indicating the linked list item as being the PCIe Capabilities
registers.
10.1.5.1.2
Next Pointer, Offset 0xE1, (RO)
Offset to the next capability item in the capability list.
10.1.5.1.3
PCI Express CAP, Offset 0xE2, (RO)
The PCIe capabilities register identifies PCIe device type and associated capabilities.
This is a read-only register.
Bits Default
R/W
3:0
0001b
RO
7:4
0000b
RO
8
0b
RO
13:9 00000b RO
15:14 00b
RO
Description
Capability Version
Indicates the PCIe capability structure version number 1.
Device/Port Type
Indicates the type of PCIe functions. LAN function in the 82583V is a native
PCIe functions with a value of 0000b.
Slot Implemented
The 82583V does not implement slot options therefore this field is hardwired
to 0b.
Interrupt Message Number
The 82583V does not implement multiple MSI per function, therefore this field
is hardwired to 0x0.
Reserved
10.1.5.1.4
Device CAP, Offset 0xE4, (RO)
This register identifies the PCIe device specific capabilities. It is a read-only register.
Bits
2:0
R/W
RO
Default
Description
001b
Max Payload Size Supported
This field indicates the maximum payload that the device can support for
TLPs. It is loaded from the NVM PCIe Init Configuration 3 word 0x1A (bit 8)
with a default value of 256 bytes.
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